diff --git a/dts/arm/96b_carbon.dts b/dts/arm/96b_carbon.dts
index 91f4e0c2247..e9fd3ccc6da 100644
--- a/dts/arm/96b_carbon.dts
+++ b/dts/arm/96b_carbon.dts
@@ -20,11 +20,15 @@
 
 &usart1 {
 	current-speed = <115200>;
+	pinctrl-0 = <&usart1_pins_b>;
+	pinctrl-names = "default";
 	status = "ok";
 };
 
 &usart2 {
 	current-speed = <115200>;
+	pinctrl-0 = <&usart2_pins_a>;
+	pinctrl-names = "default";
 	status = "ok";
 };
 
diff --git a/dts/arm/nucleo_f401re.dts b/dts/arm/nucleo_f401re.dts
index 7091306d786..feab24cb088 100644
--- a/dts/arm/nucleo_f401re.dts
+++ b/dts/arm/nucleo_f401re.dts
@@ -20,11 +20,15 @@
 
 &usart1 {
 	current-speed = <115200>;
+	pinctrl-0 = <&usart1_pins_a>;
+	pinctrl-names = "default";
 	status = "ok";
 };
 
 &usart2 {
 	current-speed = <115200>;
+	pinctrl-0 = <&usart2_pins_a>;
+	pinctrl-names = "default";
 	status = "ok";
 };
 
diff --git a/dts/arm/nucleo_f411re.dts b/dts/arm/nucleo_f411re.dts
index ca237541b9d..5180e6dae56 100644
--- a/dts/arm/nucleo_f411re.dts
+++ b/dts/arm/nucleo_f411re.dts
@@ -20,10 +20,14 @@
 
 &usart1 {
 	current-speed = <115200>;
+	pinctrl-0 = <&usart1_pins_a>;
+	pinctrl-names = "default";
 	status = "ok";
 };
 
 &usart2 {
 	current-speed = <115200>;
+	pinctrl-0 = <&usart2_pins_a>;
+	pinctrl-names = "default";
 	status = "ok";
 };
diff --git a/dts/arm/nucleo_f412zg.dts b/dts/arm/nucleo_f412zg.dts
index 0664d4ae902..de64acf8f62 100644
--- a/dts/arm/nucleo_f412zg.dts
+++ b/dts/arm/nucleo_f412zg.dts
@@ -20,5 +20,7 @@
 
 &usart3 {
 	current-speed = <115200>;
+	pinctrl-0 = <&usart3_pins_b>;
+	pinctrl-names = "default";
 	status = "ok";
 };
diff --git a/dts/arm/nucleo_f413zh.dts b/dts/arm/nucleo_f413zh.dts
index aafe940f7bf..a17c2cde4b0 100644
--- a/dts/arm/nucleo_f413zh.dts
+++ b/dts/arm/nucleo_f413zh.dts
@@ -20,5 +20,7 @@
 
 &usart3 {
 	current-speed = <115200>;
+	pinctrl-0 = <&usart3_pins_b>;
+	pinctrl-names = "default";
 	status = "ok";
 };
diff --git a/dts/arm/st/stm32f4-pinctrl.dtsi b/dts/arm/st/stm32f4-pinctrl.dtsi
new file mode 100644
index 00000000000..67ad576440a
--- /dev/null
+++ b/dts/arm/st/stm32f4-pinctrl.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller {
+			usart1_pins_a: usart1@0 {
+				rx_tx {
+					rx = <STM32_PIN_PB6 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
+					tx = <STM32_PIN_PB7 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
+				};
+			};
+			usart1_pins_b: usart1@1 {
+				rx_tx {
+					rx = <STM32_PIN_PA10 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
+					tx = <STM32_PIN_PA9 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
+				};
+			};
+			usart1_pins_c: usart1@2 {
+				rx_tx {
+					rx = <STM32_PIN_PG10 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
+					tx = <STM32_PIN_PB6 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
+				};
+			};
+			usart2_pins_a: usart2@0 {
+				rx_tx {
+					rx = <STM32_PIN_PA3 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
+					tx = <STM32_PIN_PA2 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
+				};
+			};
+			usart2_pins_b: usart2@1 {
+				rx_tx {
+					rx = <STM32_PIN_PA15 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
+					tx = <STM32_PIN_PA2 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
+				};
+			};
+			usart2_pins_c: usart2@2 {
+				rx_tx {
+					rx = <STM32_PIN_PD6 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
+					tx = <STM32_PIN_PA2 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
+				};
+			};
+			usart3_pins_a: usart3@0 {
+				rx_tx {
+					rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
+					tx = <STM32_PIN_PB10 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
+				};
+			};
+			usart3_pins_b: usart3@1 {
+				rx_tx {
+					rx = <STM32_PIN_PD9 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUPDR_NO_PULL)>;
+					tx = <STM32_PIN_PD8 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)>;
+				};
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/stm32f4.dtsi b/dts/arm/st/stm32f4.dtsi
index d7d7135cf1d..e8437eb2946 100644
--- a/dts/arm/st/stm32f4.dtsi
+++ b/dts/arm/st/stm32f4.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include <arm/armv7-m.dtsi>
+#include <st/stm32f4-pinctrl.dtsi>
 #include <st/mem.h>
 #include <dt-bindings/clock/stm32_clock.h>
 
@@ -39,6 +40,14 @@
 			label = "STM32_CLK_RCC";
 		};
 
+		pinctrl: pin-controller {
+			compatible = "st,stm32-pinmux";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40020000 0x1C00>;
+		};
+
+
 		usart1: serial@40011000 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011000 0x400>;
diff --git a/dts/arm/st/stm32f407-pinctrl.dtsi b/dts/arm/st/stm32f407-pinctrl.dtsi
new file mode 100644
index 00000000000..41f397642a6
--- /dev/null
+++ b/dts/arm/st/stm32f407-pinctrl.dtsi
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller {
+			usart3_pins_a: usart3@0 {
+				rx_tx {
+					rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+					tx = <STM32_PIN_PB10 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+				};
+			};
+			usart3_pins_b: usart3@1 {
+				rx_tx {
+					rx = <STM32_PIN_PD9 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+					tx = <STM32_PIN_PD8 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+				};
+			};
+			usart6_pins_a: usart6@0 {
+				rx_tx {
+					rx = <STM32_PIN_PG14 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+					tx = <STM32_PIN_PG9 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+				};
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/stm32f407.dtsi b/dts/arm/st/stm32f407.dtsi
index 422fbeb7ed4..6d12cd09d3f 100644
--- a/dts/arm/st/stm32f407.dtsi
+++ b/dts/arm/st/stm32f407.dtsi
@@ -4,10 +4,15 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <st/stm32f407-pinctrl.dtsi>
 #include <st/stm32f411.dtsi>
 
 / {
 	soc {
+		pinctrl: pin-controller {
+			reg = <0x40020000 0x2800>;
+		};
+
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
diff --git a/dts/arm/st/stm32f412-pinctrl.dtsi b/dts/arm/st/stm32f412-pinctrl.dtsi
new file mode 100644
index 00000000000..0b1fc6e541f
--- /dev/null
+++ b/dts/arm/st/stm32f412-pinctrl.dtsi
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller {
+			usart3_pins_a: usart3@0 {
+				rx_tx {
+					rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+					tx = <STM32_PIN_PB10 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+				};
+			};
+			usart3_pins_b: usart3@1 {
+				rx_tx {
+					rx = <STM32_PIN_PD9 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+					tx = <STM32_PIN_PD8 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+				};
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/stm32f412.dtsi b/dts/arm/st/stm32f412.dtsi
index 356e3ce80d4..1795cee1b9e 100644
--- a/dts/arm/st/stm32f412.dtsi
+++ b/dts/arm/st/stm32f412.dtsi
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <st/stm32f412-pinctrl.dtsi>
 #include <st/stm32f411.dtsi>
 
 / {
diff --git a/dts/arm/st/stm32f413-pinctrl.dtsi b/dts/arm/st/stm32f413-pinctrl.dtsi
new file mode 100644
index 00000000000..66c05ec6861
--- /dev/null
+++ b/dts/arm/st/stm32f413-pinctrl.dtsi
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2017 Florian Vaussard, HEIG-VD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller {
+			usart3_pins_a: usart3@0 {
+				rx_tx {
+					rx = <STM32_PIN_PB11 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+					tx = <STM32_PIN_PB10 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+				};
+			};
+			usart3_pins_b: usart3@1 {
+				rx_tx {
+					rx = <STM32_PIN_PD9 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+					tx = <STM32_PIN_PD8 (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)>;
+				};
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/stm32f413.dtsi b/dts/arm/st/stm32f413.dtsi
index 4dc89d3c831..a625cce3e03 100644
--- a/dts/arm/st/stm32f413.dtsi
+++ b/dts/arm/st/stm32f413.dtsi
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <st/stm32f413-pinctrl.dtsi>
 #include <st/stm32f411.dtsi>
 
 / {
diff --git a/dts/arm/st/stm32f469.dtsi b/dts/arm/st/stm32f469.dtsi
index 4d50c3d5494..d05398d6f6e 100644
--- a/dts/arm/st/stm32f469.dtsi
+++ b/dts/arm/st/stm32f469.dtsi
@@ -8,6 +8,10 @@
 
 / {
 	soc {
+		pinctrl: pin-controller {
+			reg = <0x40020000 0x2800>;
+		};
+
 		uart7: serial@40007800 {
 			compatible = "st,stm32-uart";
 			reg = <0x40007800 0x400>;
diff --git a/dts/arm/stm32f469i_disco.dts b/dts/arm/stm32f469i_disco.dts
index accca80a23c..ac09a697785 100644
--- a/dts/arm/stm32f469i_disco.dts
+++ b/dts/arm/stm32f469i_disco.dts
@@ -20,10 +20,14 @@
 
 &usart3 {
 	current-speed = <115200>;
+	pinctrl-0 = <&usart3_pins_a>;
+	pinctrl-names = "default";
 	status = "ok";
 };
 
 &usart6 {
 	current-speed = <115200>;
+	pinctrl-0 = <&usart6_pins_a>;
+	pinctrl-names = "default";
 	status = "ok";
 };
diff --git a/dts/arm/stm32f4_disco.dts b/dts/arm/stm32f4_disco.dts
index 24a03f2f7bb..b4b7f8d075b 100644
--- a/dts/arm/stm32f4_disco.dts
+++ b/dts/arm/stm32f4_disco.dts
@@ -20,10 +20,14 @@
 
 &usart1 {
 	current-speed = <115200>;
+	pinctrl-0 = <&usart1_pins_a>;
+	pinctrl-names = "default";
 	status = "ok";
 };
 
 &usart2 {
 	current-speed = <115200>;
+	pinctrl-0 = <&usart2_pins_a>;
+	pinctrl-names = "default";
 	status = "ok";
 };
diff --git a/include/dt-bindings/pinctrl/stm32-pinctrl.h b/include/dt-bindings/pinctrl/stm32-pinctrl.h
index 945f75cfdc0..6e559659791 100644
--- a/include/dt-bindings/pinctrl/stm32-pinctrl.h
+++ b/include/dt-bindings/pinctrl/stm32-pinctrl.h
@@ -56,6 +56,7 @@
 /* Usefull definitions */
 #define STM32_PUSHPULL_NOPULL    (STM32_OTYPER_PUSH_PULL | STM32_PUPDR_NO_PULL)
 #define STM32_OPENDRAIN_PULLUP   (STM32_OTYPER_OPEN_DRAIN | STM32_PUPDR_PULL_UP)
+#define STM32_PUSHPULL_PULLUP	 (STM32_OTYPER_PUSH_PULL | STM32_PUPDR_PULL_UP)
 
 /* Alternate functions numbers*/
 #define	STM32_FUNC_ALT_0 0