ITE drivers/timer: update timer_init() definition
Update timer_init() definition. Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
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c930262fd8
commit
e505f2476a
1 changed files with 42 additions and 19 deletions
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@ -54,6 +54,26 @@ static struct k_spinlock lock;
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/* Last HW count that we called sys_clock_announce() */
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static volatile uint32_t last_announced_hw_cnt;
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enum ext_timer_raw_cnt {
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EXT_NOT_RAW_CNT = 0,
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EXT_RAW_CNT,
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};
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enum ext_timer_init {
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EXT_NOT_FIRST_TIME_ENABLE = 0,
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EXT_FIRST_TIME_ENABLE,
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};
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enum ext_timer_int {
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EXT_WITHOUT_TIMER_INT = 0,
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EXT_WITH_TIMER_INT,
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};
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enum ext_timer_start {
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EXT_NOT_START_TIMER = 0,
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EXT_START_TIMER,
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};
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#ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
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static void timer_5ms_one_shot_isr(const void *unused)
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{
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@ -244,17 +264,17 @@ uint32_t sys_clock_cycle_get_32(void)
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static int timer_init(enum ext_timer_idx ext_timer,
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enum ext_clk_src_sel clock_source_sel,
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uint32_t raw,
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enum ext_timer_raw_cnt raw,
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uint32_t ms,
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uint8_t first_time_enable,
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enum ext_timer_init first_time_enable,
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uint32_t irq_num,
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uint32_t irq_flag,
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uint8_t with_int,
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uint8_t start)
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enum ext_timer_int with_int,
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enum ext_timer_start start)
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{
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uint32_t hw_cnt;
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if (raw) {
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if (raw == EXT_RAW_CNT) {
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hw_cnt = ms;
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} else {
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if (clock_source_sel == EXT_PSR_32P768K)
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@ -276,7 +296,7 @@ static int timer_init(enum ext_timer_idx ext_timer,
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return -1;
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}
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if (first_time_enable) {
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if (first_time_enable == EXT_FIRST_TIME_ENABLE) {
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/* Enable and re-start external timer x */
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IT8XXX2_EXT_CTRLX(ext_timer) |= (IT8XXX2_EXT_ETXEN |
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IT8XXX2_EXT_ETXRST);
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@ -298,12 +318,12 @@ static int timer_init(enum ext_timer_idx ext_timer,
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/* Disable external timer x */
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IT8XXX2_EXT_CTRLX(ext_timer) &= ~IT8XXX2_EXT_ETXEN;
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if (start)
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if (start == EXT_START_TIMER)
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/* Enable and re-start external timer x */
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IT8XXX2_EXT_CTRLX(ext_timer) |= (IT8XXX2_EXT_ETXEN |
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IT8XXX2_EXT_ETXRST);
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if (with_int)
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if (with_int == EXT_WITH_TIMER_INT)
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irq_enable(irq_num);
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else
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irq_disable(irq_num);
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@ -319,11 +339,12 @@ int sys_clock_driver_init(const struct device *dev)
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/* Enable 32-bit free run timer overflow interrupt */
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IRQ_CONNECT(FREE_RUN_TIMER_IRQ, 0, free_run_timer_overflow_isr, NULL,
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FREE_RUN_TIMER_FLAG);
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FREE_RUN_TIMER_FLAG);
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/* Set 32-bit timer4 for free run*/
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ret = timer_init(FREE_RUN_TIMER, EXT_PSR_32P768K, TRUE,
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FREE_RUN_TIMER_MAX_CNT, TRUE, FREE_RUN_TIMER_IRQ,
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FREE_RUN_TIMER_FLAG, TRUE, TRUE);
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ret = timer_init(FREE_RUN_TIMER, EXT_PSR_32P768K, EXT_RAW_CNT,
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FREE_RUN_TIMER_MAX_CNT, EXT_FIRST_TIME_ENABLE,
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FREE_RUN_TIMER_IRQ, FREE_RUN_TIMER_FLAG,
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EXT_WITH_TIMER_INT, EXT_START_TIMER);
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if (ret < 0) {
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LOG_ERR("Init free run timer failed");
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return ret;
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@ -332,15 +353,17 @@ int sys_clock_driver_init(const struct device *dev)
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/* Set 24-bit timer3 for timeout event */
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IRQ_CONNECT(EVENT_TIMER_IRQ, 0, evt_timer_isr, NULL, EVENT_TIMER_FLAG);
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if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, TRUE,
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EVENT_TIMER_MAX_CNT, TRUE, EVENT_TIMER_IRQ,
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EVENT_TIMER_FLAG, TRUE, FALSE);
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ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, EXT_RAW_CNT,
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EVENT_TIMER_MAX_CNT, EXT_FIRST_TIME_ENABLE,
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EVENT_TIMER_IRQ, EVENT_TIMER_FLAG,
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EXT_WITH_TIMER_INT, EXT_NOT_START_TIMER);
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} else {
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/* Start a event timer in one system tick */
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ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, TRUE,
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MAX((1 * HW_CNT_PER_SYS_TICK), 1), TRUE,
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EVENT_TIMER_IRQ, EVENT_TIMER_FLAG,
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TRUE, TRUE);
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ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, EXT_RAW_CNT,
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MAX((1 * HW_CNT_PER_SYS_TICK), 1),
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EXT_FIRST_TIME_ENABLE, EVENT_TIMER_IRQ,
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EVENT_TIMER_FLAG, EXT_WITH_TIMER_INT,
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EXT_START_TIMER);
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}
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if (ret < 0) {
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LOG_ERR("Init event timer failed");
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