michaelh/zephyr
1
0
Fork 0
Code Releases Activity

boards: nxp: imxrt700: Add documentation for i.MXRT700 DSP cores

Browse source 
Add documentation for the two HiFi1 and HiFi4 DSP cores from i.MXRT700.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
This commit is contained in:
Iuliana Prodan 2024-10-22 19:33:49 +03:00 • committed by Carles Cufí
commit e4ccfa3b2f
1 changed files with 42 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

43
boards/nxp/mimxrt700_evk/doc/index.rst
View file

@ -3,26 +3,31 @@
Overview
********
The new i.MX RT700 CPU architecture is composed of a high-performance main compute subsystem,
The new i.MX RT700 CPU architecture is composed of a high-performance main-compute subsystem,
a secondary “always-on” sense-compute subsystem and specialized coprocessors.
The main compute subsystem uses a 325 MHz capable Arm® Cortex®-M33 (CM33).
Similar to the i.MX RT600 crossover MCU, the i.MX RT700 includes a Cadence Tensilica® HiFi 4 DSP.
The main-compute subsystem has a primary Arm® Cortex®-M33 running at 325 MHz, with an integrated
Cadence® Tensilica® HiFi 4 DSP for more demanding DSP and audio processing tasks.
The sense-compute subsystem has a second Arm® Cortex®-M33 and an integrated Cadence® Tensilica®
HiFi 1 DSP. This removes the need for an external sensor hub, reducing system design complexity,
footprint and BOM costs.
The HiFi4 is a high performance DSP core based upon a Very Long Instruction Word (VLIW) architecture,
which is capable of processing up to eight 32x16 MACs per instruction cycle. It can be used for offloading
high-performance numerical tasks such as audio and image processing and supports both fixed-point and
floating-point operations.
The i.MX RT700 also features NXP’s eIQ Neutron NPU, enabled with the eIQ machine learning software
development environment.
Hardware
********
- Main Compute Subsystem:
- Arm Cortex-M33 up to 325 MHz
- HiFi 4 DSP up to 325 MHz
- eIQ Neutron NPU up to 325 MHz
- Sense Compute Subsystem:
- Arm Cortex-M33 up to 250 MHz
- HiFi 1 DSP up to 250 MHz
- 7.5 MB on-chip SRAM
@ -131,6 +136,34 @@ System Clock
The MIMXRT700 EVK is configured to use the Systick
as a source for the system clock.
HiFi1 DSP Core
==================
One can build a Zephyr application for the i.MX RT700 HiFi 1 DSP core by targeting the HiFi 1
SOC. Xtensa toolchain supporting RT700 DSP cores is included in Zephyr SDK.
To build the hello_world sample for the i.MX RT700 HiFi 1 DSP core:
.. zephyr-app-commands::
:tool: west
:zephyr-app: samples/hello_world
:board: mimxrt700_evk/mimxrt798s/hifi1
:goals: build
HiFi4 DSP Core
==================
One can build a Zephyr application for the i.MX RT700 HiFi 4 DSP core by targeting the HiFi 4
SOC. Xtensa toolchain supporting RT700 DSP cores is included in Zephyr SDK.
To build the hello_world sample for the i.MX RT700 HiFi 4 DSP core:
.. zephyr-app-commands::
:tool: west
:zephyr-app: samples/hello_world
:board: mimxrt700_evk/mimxrt798s/hifi4
:goals: build
Programming and Debugging
*************************