drivers: counter: Add ctimer driver for RT685

Add counter support using CTimer for RT685

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>

boards/arm/mimxrt685_evk/doc/index.rst

@@ -97,6 +97,8 @@ features:
 +-----------+------------+-------------------------------------+
 | ADC       | on-chip    | adc                                 |
 +-----------+------------+-------------------------------------+
+| CTIMER    | on-chip    | counter                             |
++-----------+------------+-------------------------------------+
 
 The default configuration can be found in the defconfig file:
 

boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts

@@ -310,3 +310,23 @@ i2s1: &flexcomm3 {
 zephyr_udc0: &usbhs {
 	status = "okay";
 };
+
+&ctimer0 {
+	status = "okay";
+};
+
+&ctimer1 {
+	status = "okay";
+};
+
+&ctimer2 {
+	status = "okay";
+};
+
+&ctimer3 {
+	status = "okay";
+};
+
+&ctimer4 {
+	status = "okay";
+};

dts/arm/nxp/nxp_rt6xx_common.dtsi

@@ -326,6 +326,71 @@
 		offset-value-b = <10>;
 		#io-channel-cells = <1>;
 	};
+
+	ctimer0: ctimer@28000 {
+		compatible = "nxp,lpc-ctimer";
+		reg = <0x28000 0x1000>;
+		interrupts = <10 0>;
+		status = "disabled";
+		clk-source = <1>;
+		clocks = <&clkctl1 MCUX_CTIMER0_CLK>;
+		mode = <0>;
+		input = <0>;
+		prescale = <0>;
+		label = "CTIMER_0";
+	};
+
+	ctimer1: ctimer@29000 {
+		compatible = "nxp,lpc-ctimer";
+		reg = <0x29000 0x1000>;
+		interrupts = <11 0>;
+		status = "disabled";
+		clk-source = <1>;
+		clocks = <&clkctl1 MCUX_CTIMER1_CLK>;
+		mode = <0>;
+		input = <0>;
+		prescale = <0>;
+		label = "CTIMER_1";
+	};
+
+	ctimer2: ctimer@2a000 {
+		compatible = "nxp,lpc-ctimer";
+		reg = <0x2a000 0x1000>;
+		interrupts = <39 0>;
+		status = "disabled";
+		clk-source = <1>;
+		clocks = <&clkctl1 MCUX_CTIMER2_CLK>;
+		mode = <0>;
+		input = <0>;
+		prescale = <0>;
+		label = "CTIMER_2";
+	};
+
+	ctimer3: ctimer@2b000 {
+		compatible = "nxp,lpc-ctimer";
+		reg = <0x2b000 0x1000>;
+		interrupts = <13 0>;
+		status = "disabled";
+		clk-source = <1>;
+		clocks = <&clkctl1 MCUX_CTIMER3_CLK>;
+		mode = <0>;
+		input = <0>;
+		prescale = <0>;
+		label = "CTIMER_3";
+	};
+
+	ctimer4: ctimer@2c000 {
+		compatible = "nxp,lpc-ctimer";
+		reg = <0x2c000 0x1000>;
+		interrupts = <40 0>;
+		status = "disabled";
+		clk-source = <1>;
+		clocks = <&clkctl1 MCUX_CTIMER4_CLK>;
+		mode = <0>;
+		input = <0>;
+		prescale = <0>;
+		label = "CTIMER_4";
+	};
 };
 
 &nvic {

soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.mimxrt685_cm33

@@ -74,4 +74,8 @@ choice USB_MCUX_CONTROLLER_TYPE
 	default USB_DC_NXP_LPCIP3511
 endchoice
 
+config COUNTER_MCUX_CTIMER
+	default y
+	depends on COUNTER
+
 endif # SOC_MIMXRT685S_CM33

soc/arm/nxp_imx/rt6xx/Kconfig.soc

@@ -31,7 +31,7 @@ config SOC_MIMXRT685S_CM33
 	select INIT_SYS_PLL
 	select HAS_MCUX_USB_LPCIP3511
 	select USB_DEDICATED_MEMORY if USB_DEVICE_DRIVER
-
+	select HAS_MCUX_CTIMER
 endchoice
 
 if SOC_SERIES_IMX_RT6XX

soc/arm/nxp_imx/rt6xx/soc.c

@@ -37,6 +37,12 @@
 	 (((uint32_t)nxp_rt600_init >= 0x18000000U) &&		\
 	  ((uint32_t)nxp_rt600_init < 0x20000000U)))
 
+#define CTIMER_CLOCK_SOURCE(node_id) \
+	TO_CTIMER_CLOCK_SOURCE(DT_CLOCKS_CELL(node_id, name), DT_PROP(node_id, clk_source))
+#define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val)
+#define TO_CLOCK_ATTACH_ID(inst, val) CLKCTL1_TUPLE_MUXA(CT32BIT##inst##FCLKSEL_OFFSET, val)
+#define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id));
+
 #ifdef CONFIG_INIT_SYS_PLL
 const clock_sys_pll_config_t g_sysPllConfig = {
 	.sys_pll_src  = kCLOCK_SysPllXtalIn,
@@ -269,6 +275,8 @@ static ALWAYS_INLINE void clock_init(void)
 	RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn);
 #endif
 
+	DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP)
+
 #endif /* CONFIG_SOC_MIMXRT685S_CM33 */
 }