timer: xtensa_sys_timer: set compare register at init
Since CCOMPARE* registers have undefined values after reset, set compare value first before enabling timer interrupt. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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1 changed files with 7 additions and 2 deletions
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@ -433,11 +433,16 @@ void _zxt_tick_timer_init(void)
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int val;
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__asm__ volatile("rsr.intenable %0" : "=r"(val));
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/*
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* Since CCOMPARE* registers have undefined values after reset,
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* set compare value first beforing enabling timer interrupt.
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*/
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SET_TIMER_FIRE_TIME(GET_TIMER_CURRENT_TIME() + _xt_tick_divisor);
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val |= 1 << TIMER_IRQ;
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__asm__ volatile("wsr.intenable %0" : : "r"(val));
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__asm__ volatile("rsync");
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SET_TIMER_FIRE_TIME(GET_TIMER_CURRENT_TIME() + _xt_tick_divisor);
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}
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#endif
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