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timer: xtensa_sys_timer: set compare register at init

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Since CCOMPARE* registers have undefined values after reset,
set compare value first before enabling timer interrupt.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2018-11-02 13:24:28 -07:00 • committed by Anas Nashif
commit e4aa946c55
1 changed files with 7 additions and 2 deletions
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9
drivers/timer/xtensa_sys_timer.c
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@ -433,11 +433,16 @@ void _zxt_tick_timer_init(void)
int val;
__asm__ volatile("rsr.intenable %0" : "=r"(val));
/*
* Since CCOMPARE* registers have undefined values after reset,
* set compare value first beforing enabling timer interrupt.
*/
SET_TIMER_FIRE_TIME(GET_TIMER_CURRENT_TIME() + _xt_tick_divisor);
val |= 1 << TIMER_IRQ;
__asm__ volatile("wsr.intenable %0" : : "r"(val));
__asm__ volatile("rsync");
SET_TIMER_FIRE_TIME(GET_TIMER_CURRENT_TIME() + _xt_tick_divisor);
}
#endif