dts: riscv32: rv32m1: fix reg value for cpu@1

The second cpu core has to have reg = <1>.

See, for example, dts/xtensa/esp32.dtsi.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
This commit is contained in:
Antony Pavlov 2019-05-07 09:50:34 +03:00 committed by Anas Nashif
commit e44052f25a

View file

@ -46,7 +46,7 @@
cpu@1 {
device_type = "cpu";
compatible = "riscv";
reg = <0>;
reg = <1>;
};
};