dts: riscv32: rv32m1: fix reg value for cpu@1
The second cpu core has to have reg = <1>. See, for example, dts/xtensa/esp32.dtsi. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
This commit is contained in:
parent
42bdcccd97
commit
e44052f25a
1 changed files with 1 additions and 1 deletions
|
@ -46,7 +46,7 @@
|
|||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "riscv";
|
||||
reg = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue