michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: usdhc: fixup i.MX RT related code after driver relocation

Browse source 
Fixup i.MX RT related code after driver relocation.

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
This commit is contained in:
Johann Fischer 2021-02-24 11:07:56 +01:00 • committed by Carles Cufí
commit e3e25d0a58
12 changed files with 20 additions and 40 deletions
Download patch file Download diff file Expand all files Collapse all files

4
boards/arm/mimxrt1050_evk/Kconfig.defconfig
View file

@ -12,10 +12,6 @@ choice CODE_LOCATION
default CODE_FLEXSPI default CODE_FLEXSPI
endchoice endchoice
config DISK_ACCESS_USDHC1
default y
depends on DISK_ACCESS_USDHC
config I2C config I2C
default y if KSCAN default y if KSCAN

4
boards/arm/mimxrt1050_evk/pinmux.c
View file

@ -17,7 +17,7 @@ static gpio_pin_config_t enet_gpio_config = {
}; };
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_ACCESS_USDHC1 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
/*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) /*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
*Speed Field: medium(100MHz) *Speed Field: medium(100MHz)
@ -310,7 +310,7 @@ static int mimxrt1050_evk_init(const struct device *dev)
GPIO_PinInit(GPIO2, 31, &config); GPIO_PinInit(GPIO2, 31, &config);
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_ACCESS_USDHC1 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
mimxrt1050_evk_usdhc_pinmux(0, true, 2, 1); mimxrt1050_evk_usdhc_pinmux(0, true, 2, 1);
imxrt_usdhc_pinmux_cb_register(mimxrt1050_evk_usdhc_pinmux); imxrt_usdhc_pinmux_cb_register(mimxrt1050_evk_usdhc_pinmux);
#endif #endif

4
boards/arm/mimxrt1060_evk/Kconfig.defconfig
View file

@ -13,10 +13,6 @@ choice CODE_LOCATION
default CODE_FLEXSPI default CODE_FLEXSPI
endchoice endchoice
config DISK_ACCESS_USDHC1
default y
depends on DISK_ACCESS_USDHC
config I2C config I2C
default y if KSCAN default y if KSCAN

4
boards/arm/mimxrt1060_evk/pinmux.c
View file

@ -20,7 +20,7 @@ static gpio_pin_config_t enet_gpio_config = {
}; };
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_ACCESS_USDHC1 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
/*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) /*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
*Speed Field: medium(100MHz) *Speed Field: medium(100MHz)
@ -292,7 +292,7 @@ static int mimxrt1060_evk_init(const struct device *dev)
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_37_FLEXCAN3_RX, 0x10B0u); IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_37_FLEXCAN3_RX, 0x10B0u);
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_ACCESS_USDHC1 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
mimxrt1060_evk_usdhc_pinmux(0, true, 2, 1); mimxrt1060_evk_usdhc_pinmux(0, true, 2, 1);
imxrt_usdhc_pinmux_cb_register(mimxrt1060_evk_usdhc_pinmux); imxrt_usdhc_pinmux_cb_register(mimxrt1060_evk_usdhc_pinmux);
#endif #endif

4
boards/arm/mimxrt1064_evk/Kconfig.defconfig
View file

@ -12,10 +12,6 @@ choice CODE_LOCATION
default CODE_FLEXSPI2 default CODE_FLEXSPI2
endchoice endchoice
config DISK_ACCESS_USDHC1
default y
depends on DISK_ACCESS_USDHC
config FLASH_MCUX_FLEXSPI_NOR config FLASH_MCUX_FLEXSPI_NOR
default y if FLASH default y if FLASH

4
boards/arm/mimxrt1064_evk/pinmux.c
View file

@ -20,7 +20,7 @@ static gpio_pin_config_t enet_gpio_config = {
}; };
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_ACCESS_USDHC1 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
/*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) /*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
*Speed Field: medium(100MHz) *Speed Field: medium(100MHz)
@ -296,7 +296,7 @@ static int mimxrt1064_evk_init(const struct device *dev)
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_37_FLEXCAN3_RX, 0x10B0u); IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_37_FLEXCAN3_RX, 0x10B0u);
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_ACCESS_USDHC1 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
mimxrt1064_evk_usdhc_pinmux(0, true, 2, 1); mimxrt1064_evk_usdhc_pinmux(0, true, 2, 1);
imxrt_usdhc_pinmux_cb_register(mimxrt1064_evk_usdhc_pinmux); imxrt_usdhc_pinmux_cb_register(mimxrt1064_evk_usdhc_pinmux);
#endif #endif

4
boards/arm/mm_swiftio/Kconfig.defconfig
View file

@ -12,8 +12,4 @@ choice CODE_LOCATION
default CODE_FLEXSPI default CODE_FLEXSPI
endchoice endchoice
config DISK_ACCESS_USDHC1
default y
depends on DISK_ACCESS_USDHC
endif # BOARD_MM_SWIFTIO endif # BOARD_MM_SWIFTIO

4
boards/arm/mm_swiftio/pinmux.c
View file

@ -17,7 +17,7 @@ static gpio_pin_config_t enet_gpio_config = {
}; };
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_ACCESS_USDHC1 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
/*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) /*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
* Speed Field: medium(100MHz) * Speed Field: medium(100MHz)
@ -187,7 +187,7 @@ static int mm_swiftio_init(const struct device *dev)
IOMUXC_SW_PAD_CTL_PAD_DSE(6)); IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_ACCESS_USDHC1 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
mm_swiftio_usdhc_pinmux(0, true, 2, 1); mm_swiftio_usdhc_pinmux(0, true, 2, 1);
imxrt_usdhc_pinmux_cb_register(mm_swiftio_usdhc_pinmux); imxrt_usdhc_pinmux_cb_register(mm_swiftio_usdhc_pinmux);
#endif #endif

4
drivers/clock_control/clock_control_mcux_ccm.c
View file

@ -82,14 +82,14 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
break; break;
#endif #endif
#ifdef CONFIG_DISK_ACCESS_USDHC1 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
case IMX_CCM_USDHC1_CLK: case IMX_CCM_USDHC1_CLK:
*rate = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / *rate = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) /
(CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U); (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U);
break; break;
#endif #endif
#ifdef CONFIG_DISK_ACCESS_USDHC2 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) && CONFIG_DISK_DRIVER_SDMMC
case IMX_CCM_USDHC2_CLK: case IMX_CCM_USDHC2_CLK:
*rate = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / *rate = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) /
(CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U); (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U);

4
soc/arm/nxp_imx/rt/Kconfig.defconfig.series
View file

@ -19,10 +19,6 @@ config CLOCK_CONTROL_MCUX_CCM
default y if HAS_MCUX_CCM default y if HAS_MCUX_CCM
depends on CLOCK_CONTROL depends on CLOCK_CONTROL
config DISK_ACCESS_USDHC
default y if (HAS_MCUX_USDHC1 || HAS_MCUX_USDHC2)
depends on DISK_ACCESS_SDHC
config DISPLAY_MCUX_ELCDIF config DISPLAY_MCUX_ELCDIF
default y if HAS_MCUX_ELCDIF default y if HAS_MCUX_ELCDIF
depends on DISPLAY depends on DISPLAY

15
soc/arm/nxp_imx/rt/soc.c
View file

@ -191,21 +191,21 @@ static ALWAYS_INLINE void clock_init(void)
USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig); USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig);
#endif #endif
#if defined(CONFIG_DISK_ACCESS_USDHC1) || \ #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
defined(CONFIG_DISK_ACCESS_USDHC2)
CLOCK_InitSysPfd(kCLOCK_Pfd0, 0x12U);
/* Configure USDHC clock source and divider */ /* Configure USDHC clock source and divider */
#ifdef CONFIG_DISK_ACCESS_USDHC1 CLOCK_InitSysPfd(kCLOCK_Pfd0, 0x12U);
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 0U); CLOCK_SetDiv(kCLOCK_Usdhc1Div, 0U);
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U); CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);
CLOCK_EnableClock(kCLOCK_Usdhc1); CLOCK_EnableClock(kCLOCK_Usdhc1);
#endif #endif
#ifdef CONFIG_DISK_ACCESS_USDHC2 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) && CONFIG_DISK_DRIVER_SDMMC
/* Configure USDHC clock source and divider */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 0x12U);
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 0U); CLOCK_SetDiv(kCLOCK_Usdhc2Div, 0U);
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 1U); CLOCK_SetMux(kCLOCK_Usdhc2Mux, 1U);
CLOCK_EnableClock(kCLOCK_Usdhc2); CLOCK_EnableClock(kCLOCK_Usdhc2);
#endif #endif
#endif
#ifdef CONFIG_VIDEO_MCUX_CSI #ifdef CONFIG_VIDEO_MCUX_CSI
CLOCK_EnableClock(kCLOCK_Csi); /* Disable CSI clock gate */ CLOCK_EnableClock(kCLOCK_Csi); /* Disable CSI clock gate */
CLOCK_SetDiv(kCLOCK_CsiDiv, 0); /* Set CSI divider to 1 */ CLOCK_SetDiv(kCLOCK_CsiDiv, 0); /* Set CSI divider to 1 */
@ -230,8 +230,7 @@ static ALWAYS_INLINE void clock_init(void)
} }
#if defined(CONFIG_DISK_ACCESS_USDHC1) || \ #if (DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC)
defined(CONFIG_DISK_ACCESS_USDHC2)
/* Usdhc driver needs to re-configure pinmux /* Usdhc driver needs to re-configure pinmux
* Pinmux depends on board design. * Pinmux depends on board design.

5
soc/arm/nxp_imx/rt/soc.h
View file

@ -20,8 +20,9 @@
extern "C" { extern "C" {
#endif #endif
#if defined(CONFIG_DISK_ACCESS_USDHC1) || \ #if CONFIG_DISK_DRIVER_SDMMC && \
defined(CONFIG_DISK_ACCESS_USDHC2) (DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) || \
DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay))
typedef void (*usdhc_pin_cfg_cb)(uint16_t nusdhc, bool init, typedef void (*usdhc_pin_cfg_cb)(uint16_t nusdhc, bool init,
uint32_t speed, uint32_t strength); uint32_t speed, uint32_t strength);