arch: riscv: pmp: introduce riscv_pmp_region structure
Using struct riscv_pmp_region to modulize PMP CSR handling, including PMP NAPOT/TOR mode handling. This patch can make us more easily to add/remove RISC-V PMP regions without considering register handling. Signed-off-by: Jim Shu <cwshu@andestech.com>
This commit is contained in:
Jim Shu
Carles Cufí
parent
e4c5d96a8b
commit
e3c8b4cae4
2 changed files with 309 additions and 140 deletions
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@ -15,12 +15,54 @@
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#include <logging/log.h>
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LOG_MODULE_REGISTER(mpu);
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#define PMP_SLOT_NUMBER CONFIG_PMP_SLOT
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#ifdef CONFIG_64BIT
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# define PR_ADDR "0x%016lx"
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#else
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# define PR_ADDR "0x%08lx"
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#endif
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#ifdef CONFIG_64BIT
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# define PMPCFG_NUM(index) (((index) / 8) * 2)
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# define PMPCFG_SHIFT(index) (((index) % 8) * 8)
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#else
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# define PMPCFG_NUM(index) ((index) / 4)
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# define PMPCFG_SHIFT(index) (((index) % 4) * 8)
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#endif
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#if defined(CONFIG_PMP_POWER_OF_TWO_ALIGNMENT)
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# define PMP_MODE_DEFAULT PMP_MODE_NAPOT
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#else
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# define PMP_MODE_DEFAULT PMP_MODE_TOR
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#endif
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enum pmp_region_mode {
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PMP_MODE_NA4,
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/* If NAPOT mode region size is 4, apply NA4 region to PMP CSR. */
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PMP_MODE_NAPOT,
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PMP_MODE_TOR,
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};
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/* Region definition data structure */
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struct riscv_pmp_region {
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ulong_t start;
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ulong_t size;
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uint8_t perm;
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enum pmp_region_mode mode;
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};
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#ifdef CONFIG_USERSPACE
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extern ulong_t is_user_mode;
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#endif
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#ifdef CONFIG_PMP_STACK_GUARD
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static const struct riscv_pmp_region irq_stack_guard_region = {
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.start = (ulong_t) z_interrupt_stacks[0],
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.size = PMP_GUARD_ALIGN_AND_SIZE,
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.perm = 0,
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.mode = PMP_MODE_NAPOT,
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};
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#endif
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enum {
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CSR_PMPCFG0,
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CSR_PMPCFG1,
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@ -44,7 +86,7 @@ enum {
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CSR_PMPADDR15
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};
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static ulong_t csr_read_enum(int pmp_csr_enum)
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static __unused ulong_t csr_read_enum(int pmp_csr_enum)
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{
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ulong_t res = -1;
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@ -143,44 +185,203 @@ static void csr_write_enum(int pmp_csr_enum, ulong_t value)
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}
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}
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int z_riscv_pmp_set(unsigned int index, ulong_t cfg_val, ulong_t addr_val)
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/*
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* @brief Set a Physical Memory Protection slot
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*
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* Configure a memory region to be secured by one of the 16 PMP entries.
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*
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* @param index Number of the targeted PMP entrie (0 to 15 only).
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* @param cfg_val Configuration value (cf datasheet or defined flags)
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* @param addr_val Address register value
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*
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* This function shall only be called from Secure state.
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*
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* @return -1 if bad argument, 0 otherwise.
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*/
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static __unused int riscv_pmp_set(unsigned int index, ulong_t cfg_val, ulong_t addr_val)
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{
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ulong_t reg_val;
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ulong_t shift, mask;
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int pmpcfg_csr;
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int pmpaddr_csr;
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if (index >= PMP_SLOT_NUMBER) {
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if (index >= CONFIG_PMP_SLOT) {
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return -1;
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}
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/* Calculate PMP config/addr register, shift and mask */
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#ifdef CONFIG_64BIT
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pmpcfg_csr = CSR_PMPCFG0 + ((index >> 3) << 1);
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shift = (index & 0x7) << 3;
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#else
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pmpcfg_csr = CSR_PMPCFG0 + (index >> 2);
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shift = (index & 0x3) << 3;
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#endif /* CONFIG_64BIT */
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pmpcfg_csr = CSR_PMPCFG0 + PMPCFG_NUM(index);
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pmpaddr_csr = CSR_PMPADDR0 + index;
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/* Mask = 0x000000FF<<((index%4)*8) */
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mask = 0x000000FF << shift;
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cfg_val = cfg_val << shift;
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addr_val = TO_PMP_ADDR(addr_val);
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shift = PMPCFG_SHIFT(index);
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mask = 0xFF << shift;
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reg_val = csr_read_enum(pmpcfg_csr);
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reg_val = reg_val & ~mask;
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reg_val = reg_val | cfg_val;
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reg_val = reg_val | (cfg_val << shift);
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csr_write_enum(pmpaddr_csr, addr_val);
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csr_write_enum(pmpcfg_csr, reg_val);
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return 0;
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}
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static int riscv_pmp_region_translate(int index,
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const struct riscv_pmp_region *region, bool to_csr,
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ulong_t pmpcfg[], ulong_t pmpaddr[])
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{
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int result, pmp_mode;
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if ((region->start == 0) && (region->size == 0)) {
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/* special case: set whole memory as single PMP region.
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* RV32: 0 ~ (2**32 - 1)
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* RV64: 0 ~ (2**64 - 1)
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*/
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if (index >= CONFIG_PMP_SLOT) {
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return -ENOSPC;
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}
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pmp_mode = PMP_NAPOT;
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uint8_t cfg_val = PMP_NAPOT | region->perm;
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#ifdef CONFIG_64BIT
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ulong_t addr_val = 0x1FFFFFFFFFFFFFFF;
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#else
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ulong_t addr_val = 0x1FFFFFFF;
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#endif
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if (to_csr) {
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riscv_pmp_set(index, cfg_val, addr_val);
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} else {
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uint8_t *u8_pmpcfg = (uint8_t *)pmpcfg;
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u8_pmpcfg[index] = cfg_val;
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pmpaddr[index] = addr_val;
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}
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result = index+1;
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} else if (region->mode == PMP_MODE_TOR) {
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if ((index+1) >= CONFIG_PMP_SLOT) {
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return -ENOSPC;
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}
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pmp_mode = PMP_TOR;
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uint8_t cfg_val1 = PMP_NA4 | region->perm;
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ulong_t addr_val1 = TO_PMP_ADDR(region->start);
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uint8_t cfg_val2 = PMP_TOR | region->perm;
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ulong_t addr_val2 = TO_PMP_ADDR(region->start + region->size);
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if (to_csr) {
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riscv_pmp_set(index, cfg_val1, addr_val1);
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riscv_pmp_set(index+1, cfg_val2, addr_val2);
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} else {
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uint8_t *u8_pmpcfg = (uint8_t *)pmpcfg;
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u8_pmpcfg[index] = cfg_val1;
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pmpaddr[index] = addr_val1;
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u8_pmpcfg[index+1] = cfg_val2;
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pmpaddr[index+1] = addr_val2;
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}
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result = index+2;
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} else {
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if (index >= CONFIG_PMP_SLOT) {
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return -ENOSPC;
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}
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if ((region->mode == PMP_MODE_NA4) || (region->size == 4)) {
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pmp_mode = PMP_NA4;
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} else {
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pmp_mode = PMP_NAPOT;
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}
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uint8_t cfg_val = pmp_mode | region->perm;
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ulong_t addr_val = TO_PMP_NAPOT(region->start, region->size);
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if (to_csr) {
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riscv_pmp_set(index, cfg_val, addr_val);
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} else {
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uint8_t *u8_pmpcfg = (uint8_t *)pmpcfg;
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u8_pmpcfg[index] = cfg_val;
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pmpaddr[index] = addr_val;
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}
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result = index+1;
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}
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if (to_csr) {
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LOG_DBG("Set PMP region %d: (" PR_ADDR ", " PR_ADDR
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", %s%s%s, %s)", index, region->start, region->size,
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((region->perm & PMP_R) ? "R" : " "),
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((region->perm & PMP_W) ? "W" : " "),
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((region->perm & PMP_X) ? "X" : " "),
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((pmp_mode == PMP_TOR) ? "TOR" :
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(pmp_mode == PMP_NAPOT) ? "NAPOT" : "NA4"));
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} else {
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LOG_DBG("PMP context " PR_ADDR " add region %d: (" PR_ADDR
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", " PR_ADDR ", %s%s%s, %s)", (ulong_t) pmpcfg, index,
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region->start, region->size,
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((region->perm & PMP_R) ? "R" : " "),
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((region->perm & PMP_W) ? "W" : " "),
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((region->perm & PMP_X) ? "X" : " "),
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((pmp_mode == PMP_TOR) ? "TOR" :
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(pmp_mode == PMP_NAPOT) ? "NAPOT" : "NA4"));
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}
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if (pmp_mode == PMP_TOR) {
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LOG_DBG("TOR mode region also use entry %d", index+1);
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}
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return result;
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}
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#if defined(CONFIG_PMP_STACK_GUARD) || defined(CONFIG_USERSPACE)
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static __unused int riscv_pmp_regions_translate(int start_reg_index,
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const struct riscv_pmp_region regions[], uint8_t regions_num,
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ulong_t pmpcfg[], ulong_t pmpaddr[])
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{
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int reg_index = start_reg_index;
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for (int i = 0; i < regions_num; i++) {
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/*
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* Empty region.
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*
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* Note: start = size = 0 is valid region (special case).
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*/
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if ((regions[i].size == 0U) && (regions[i].start != 0)) {
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continue;
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}
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/* Non-empty region. */
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reg_index = riscv_pmp_region_translate(reg_index, ®ions[i],
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false, pmpcfg, pmpaddr);
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if (reg_index == -ENOSPC) {
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LOG_ERR("no free PMP entry");
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return -ENOSPC;
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}
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}
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return reg_index;
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}
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#endif /* defined(CONFIG_PMP_STACK_GUARD) || defined(CONFIG_USERSPACE) */
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static int riscv_pmp_region_set(int index, const struct riscv_pmp_region *region)
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{
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/* Check 4 bytes alignment */
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CHECKIF(!(((region->start & 0x3) == 0) &&
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((region->size & 0x3) == 0) &&
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region->size)) {
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LOG_ERR("PMP address/size are not 4 bytes aligned");
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return -EINVAL;
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}
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return riscv_pmp_region_translate(index, region, true, NULL, NULL);
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}
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void z_riscv_pmp_clear_config(void)
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{
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LOG_DBG("Clear all dynamic PMP regions");
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for (unsigned int i = 0; i < RISCV_PMP_CFG_NUM; i++)
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csr_write_enum(CSR_PMPCFG0 + i, 0);
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}
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@ -189,48 +390,38 @@ void z_riscv_pmp_clear_config(void)
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#include <linker/linker-defs.h>
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void z_riscv_init_user_accesses(struct k_thread *thread)
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{
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unsigned char index;
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unsigned char *uchar_pmpcfg;
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ulong_t rom_start = (ulong_t) __rom_region_start;
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#if defined(CONFIG_PMP_POWER_OF_TWO_ALIGNMENT)
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ulong_t rom_size = (ulong_t) __rom_region_size;
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#else /* CONFIG_PMP_POWER_OF_TWO_ALIGNMENT */
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ulong_t rom_end = (ulong_t) __rom_region_end;
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#endif /* CONFIG_PMP_POWER_OF_TWO_ALIGNMENT */
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index = 0U;
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uchar_pmpcfg = (unsigned char *) thread->arch.u_pmpcfg;
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unsigned char index = 0U;
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#ifdef CONFIG_PMP_STACK_GUARD
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index++;
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#endif /* CONFIG_PMP_STACK_GUARD */
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struct riscv_pmp_region dynamic_regions[] = {
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{
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/* MCU state */
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thread->arch.u_pmpaddr[index] = TO_PMP_ADDR((ulong_t) &is_user_mode);
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uchar_pmpcfg[index++] = PMP_NA4 | PMP_R;
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#if defined(CONFIG_PMP_POWER_OF_TWO_ALIGNMENT)
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.start = (ulong_t) &is_user_mode,
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.size = 4,
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.perm = PMP_R,
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.mode = PMP_MODE_NA4,
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},
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{
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/* Program and RO data */
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thread->arch.u_pmpaddr[index] = TO_PMP_NAPOT(rom_start, rom_size);
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uchar_pmpcfg[index++] = PMP_NAPOT | PMP_R | PMP_X;
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.start = (ulong_t) __rom_region_start,
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.size = (ulong_t) __rom_region_size,
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.perm = PMP_R | PMP_X,
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.mode = PMP_MODE_DEFAULT,
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},
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{
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/* User-mode thread stack */
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.start = thread->stack_info.start,
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.size = thread->stack_info.size,
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.perm = PMP_R | PMP_W,
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.mode = PMP_MODE_DEFAULT,
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},
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};
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/* RAM */
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thread->arch.u_pmpaddr[index] = TO_PMP_NAPOT(thread->stack_info.start,
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thread->stack_info.size);
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uchar_pmpcfg[index++] = PMP_NAPOT | PMP_R | PMP_W;
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#else /* CONFIG_PMP_POWER_OF_TWO_ALIGNMENT */
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/* Program and RO data */
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thread->arch.u_pmpaddr[index] = TO_PMP_ADDR(rom_start);
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uchar_pmpcfg[index++] = PMP_NA4 | PMP_R | PMP_X;
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thread->arch.u_pmpaddr[index] = TO_PMP_ADDR(rom_end);
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uchar_pmpcfg[index++] = PMP_TOR | PMP_R | PMP_X;
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/* RAM */
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thread->arch.u_pmpaddr[index] = TO_PMP_ADDR(thread->stack_info.start);
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uchar_pmpcfg[index++] = PMP_NA4 | PMP_R | PMP_W;
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thread->arch.u_pmpaddr[index] = TO_PMP_ADDR(thread->stack_info.start +
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thread->stack_info.size);
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uchar_pmpcfg[index++] = PMP_TOR | PMP_R | PMP_W;
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#endif /* CONFIG_PMP_POWER_OF_TWO_ALIGNMENT */
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riscv_pmp_regions_translate(index, dynamic_regions,
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ARRAY_SIZE(dynamic_regions), thread->arch.u_pmpcfg,
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thread->arch.u_pmpaddr);
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}
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void z_riscv_configure_user_allowed_stack(struct k_thread *thread)
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@ -244,6 +435,9 @@ void z_riscv_configure_user_allowed_stack(struct k_thread *thread)
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for (i = 0U; i < RISCV_PMP_CFG_NUM; i++)
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csr_write_enum(CSR_PMPCFG0 + i, thread->arch.u_pmpcfg[i]);
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LOG_DBG("Apply user PMP context " PR_ADDR " to dynamic PMP regions",
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(ulong_t) thread->arch.u_pmpcfg);
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}
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int z_riscv_pmp_add_dynamic(struct k_thread *thread,
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@ -262,6 +456,12 @@ int z_riscv_pmp_add_dynamic(struct k_thread *thread,
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goto out;
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}
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struct riscv_pmp_region pmp_region = {
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.start = addr,
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.size = size,
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.perm = flags,
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};
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/* Get next free entry */
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uchar_pmpcfg = (unsigned char *) thread->arch.u_pmpcfg;
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@ -271,35 +471,18 @@ int z_riscv_pmp_add_dynamic(struct k_thread *thread,
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index++;
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}
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__ASSERT((index < CONFIG_PMP_SLOT), "no free PMP entry\n");
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CHECKIF(!(index < CONFIG_PMP_SLOT)) {
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ret = -ENOSPC;
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goto out;
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}
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/* Select the best type */
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/* Select the best mode */
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if (size == 4) {
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thread->arch.u_pmpaddr[index] = TO_PMP_ADDR(addr);
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uchar_pmpcfg[index] = flags | PMP_NA4;
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}
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#if !defined(CONFIG_PMP_POWER_OF_TWO_ALIGNMENT)
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else if ((addr & (size - 1)) || (size & (size - 1))) {
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__ASSERT(((index + 1) < CONFIG_PMP_SLOT),
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"not enough free PMP entries\n");
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CHECKIF(!((index + 1) < CONFIG_PMP_SLOT)) {
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ret = -ENOSPC;
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goto out;
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pmp_region.mode = PMP_MODE_NA4;
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} else {
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pmp_region.mode = PMP_MODE_DEFAULT;
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}
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thread->arch.u_pmpaddr[index] = TO_PMP_ADDR(addr);
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uchar_pmpcfg[index++] = flags | PMP_NA4;
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thread->arch.u_pmpaddr[index] = TO_PMP_ADDR(addr + size);
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uchar_pmpcfg[index++] = flags | PMP_TOR;
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}
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#endif /* !CONFIG_PMP_POWER_OF_TWO_ALIGNMENT */
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else {
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thread->arch.u_pmpaddr[index] = TO_PMP_NAPOT(addr, size);
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uchar_pmpcfg[index] = flags | PMP_NAPOT;
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index = riscv_pmp_region_translate(index, &pmp_region, false,
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thread->arch.u_pmpcfg, thread->arch.u_pmpaddr);
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if (index == -ENOSPC) {
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ret = -ENOSPC;
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}
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out:
|
||||
|
|
@ -396,7 +579,7 @@ int arch_mem_domain_partition_remove(struct k_mem_domain *domain,
|
|||
{
|
||||
sys_dnode_t *node, *next_node;
|
||||
uint32_t index, i, num;
|
||||
ulong_t pmp_type, pmp_addr;
|
||||
ulong_t pmp_mode, pmp_addr;
|
||||
unsigned char *uchar_pmpcfg;
|
||||
struct k_thread *thread;
|
||||
ulong_t size = (ulong_t) domain->partitions[partition_id].size;
|
||||
|
|
@ -416,19 +599,19 @@ int arch_mem_domain_partition_remove(struct k_mem_domain *domain,
|
|||
}
|
||||
|
||||
if (size == 4) {
|
||||
pmp_type = PMP_NA4;
|
||||
pmp_mode = PMP_NA4;
|
||||
pmp_addr = TO_PMP_ADDR(start);
|
||||
num = 1U;
|
||||
}
|
||||
#if !defined(CONFIG_PMP_POWER_OF_TWO_ALIGNMENT) || defined(CONFIG_PMP_STACK_GUARD)
|
||||
else if ((start & (size - 1)) || (size & (size - 1))) {
|
||||
pmp_type = PMP_TOR;
|
||||
pmp_mode = PMP_TOR;
|
||||
pmp_addr = TO_PMP_ADDR(start + size);
|
||||
num = 2U;
|
||||
}
|
||||
#endif /* CONFIG_PMP_POWER_OF_TWO_ALIGNMENT || CONFIG_PMP_STACK_GUARD */
|
||||
else {
|
||||
pmp_type = PMP_NAPOT;
|
||||
pmp_mode = PMP_NAPOT;
|
||||
pmp_addr = TO_PMP_NAPOT(start, size);
|
||||
num = 1U;
|
||||
}
|
||||
|
|
@ -442,7 +625,7 @@ int arch_mem_domain_partition_remove(struct k_mem_domain *domain,
|
|||
for (index = PMP_REGION_NUM_FOR_U_THREAD;
|
||||
index < CONFIG_PMP_SLOT;
|
||||
index++) {
|
||||
if (((uchar_pmpcfg[index] & PMP_TYPE_MASK) == pmp_type) &&
|
||||
if (((uchar_pmpcfg[index] & PMP_TYPE_MASK) == pmp_mode) &&
|
||||
(pmp_addr == thread->arch.u_pmpaddr[index])) {
|
||||
break;
|
||||
}
|
||||
|
|
@ -460,7 +643,7 @@ int arch_mem_domain_partition_remove(struct k_mem_domain *domain,
|
|||
* using this memory domain.
|
||||
*/
|
||||
#if !defined(CONFIG_PMP_POWER_OF_TWO_ALIGNMENT) || defined(CONFIG_PMP_STACK_GUARD)
|
||||
if (pmp_type == PMP_TOR) {
|
||||
if (pmp_mode == PMP_TOR) {
|
||||
index--;
|
||||
}
|
||||
#endif /* CONFIG_PMP_POWER_OF_TWO_ALIGNMENT || CONFIG_PMP_STACK_GUARD */
|
||||
|
|
@ -554,24 +737,18 @@ int arch_mem_domain_thread_remove(struct k_thread *thread)
|
|||
#endif /* CONFIG_USERSPACE */
|
||||
|
||||
#ifdef CONFIG_PMP_STACK_GUARD
|
||||
|
||||
void z_riscv_init_stack_guard(struct k_thread *thread)
|
||||
{
|
||||
unsigned char index = 0U;
|
||||
unsigned char *uchar_pmpcfg;
|
||||
ulong_t stack_guard_addr;
|
||||
|
||||
uchar_pmpcfg = (unsigned char *) thread->arch.s_pmpcfg;
|
||||
|
||||
uchar_pmpcfg++;
|
||||
struct riscv_pmp_region dynamic_regions[4]; /* Maximum region_num is 4 */
|
||||
uint8_t region_num = 0U;
|
||||
|
||||
/* stack guard: None */
|
||||
thread->arch.s_pmpaddr[index] = TO_PMP_ADDR(thread->stack_info.start);
|
||||
uchar_pmpcfg[index++] = PMP_NA4;
|
||||
thread->arch.s_pmpaddr[index] =
|
||||
TO_PMP_ADDR(thread->stack_info.start +
|
||||
PMP_GUARD_ALIGN_AND_SIZE);
|
||||
uchar_pmpcfg[index++] = PMP_TOR;
|
||||
dynamic_regions[region_num].start = thread->stack_info.start;
|
||||
dynamic_regions[region_num].size = PMP_GUARD_ALIGN_AND_SIZE;
|
||||
dynamic_regions[region_num].perm = 0;
|
||||
dynamic_regions[region_num].mode = PMP_MODE_TOR;
|
||||
region_num++;
|
||||
|
||||
#ifdef CONFIG_USERSPACE
|
||||
if (thread->arch.priv_stack_start) {
|
||||
|
|
@ -580,28 +757,34 @@ void z_riscv_init_stack_guard(struct k_thread *thread)
|
|||
#else
|
||||
stack_guard_addr = (ulong_t) thread->stack_obj;
|
||||
#endif /* CONFIG_PMP_POWER_OF_TWO_ALIGNMENT */
|
||||
thread->arch.s_pmpaddr[index] =
|
||||
TO_PMP_ADDR(stack_guard_addr);
|
||||
uchar_pmpcfg[index++] = PMP_NA4;
|
||||
thread->arch.s_pmpaddr[index] =
|
||||
TO_PMP_ADDR(stack_guard_addr +
|
||||
PMP_GUARD_ALIGN_AND_SIZE);
|
||||
uchar_pmpcfg[index++] = PMP_TOR;
|
||||
dynamic_regions[region_num].start = stack_guard_addr;
|
||||
dynamic_regions[region_num].size = PMP_GUARD_ALIGN_AND_SIZE;
|
||||
dynamic_regions[region_num].perm = 0;
|
||||
dynamic_regions[region_num].mode = PMP_MODE_TOR;
|
||||
region_num++;
|
||||
}
|
||||
#endif /* CONFIG_USERSPACE */
|
||||
|
||||
/* RAM: RW */
|
||||
thread->arch.s_pmpaddr[index] = TO_PMP_ADDR(CONFIG_SRAM_BASE_ADDRESS |
|
||||
TO_NAPOT_RANGE(KB(CONFIG_SRAM_SIZE)));
|
||||
uchar_pmpcfg[index++] = (PMP_NAPOT | PMP_R | PMP_W);
|
||||
dynamic_regions[region_num].start = CONFIG_SRAM_BASE_ADDRESS;
|
||||
dynamic_regions[region_num].size = KB(CONFIG_SRAM_SIZE);
|
||||
dynamic_regions[region_num].perm = PMP_R | PMP_W;
|
||||
dynamic_regions[region_num].mode = PMP_MODE_NAPOT;
|
||||
region_num++;
|
||||
|
||||
/* All other memory: RWX */
|
||||
#ifdef CONFIG_64BIT
|
||||
thread->arch.s_pmpaddr[index] = 0x1FFFFFFFFFFFFFFF;
|
||||
#else
|
||||
thread->arch.s_pmpaddr[index] = 0x1FFFFFFF;
|
||||
#endif /* CONFIG_64BIT */
|
||||
uchar_pmpcfg[index] = PMP_NAPOT | PMP_R | PMP_W | PMP_X;
|
||||
/* special case: start = size = 0 means whole memory. */
|
||||
dynamic_regions[region_num].start = 0;
|
||||
dynamic_regions[region_num].size = 0;
|
||||
dynamic_regions[region_num].perm = PMP_R | PMP_W | PMP_X;
|
||||
dynamic_regions[region_num].mode = PMP_MODE_NAPOT;
|
||||
region_num++;
|
||||
|
||||
/* Reserve index 0 for PMP stack guard */
|
||||
unsigned char index = 1;
|
||||
|
||||
riscv_pmp_regions_translate(index, dynamic_regions, region_num,
|
||||
thread->arch.s_pmpcfg, thread->arch.s_pmpaddr);
|
||||
}
|
||||
|
||||
void z_riscv_configure_stack_guard(struct k_thread *thread)
|
||||
|
|
@ -613,8 +796,8 @@ void z_riscv_configure_stack_guard(struct k_thread *thread)
|
|||
|
||||
z_riscv_pmp_clear_config();
|
||||
|
||||
for (i = 0U; i < PMP_REGION_NUM_FOR_STACK_GUARD; i++)
|
||||
csr_write_enum(CSR_PMPADDR1 + i, thread->arch.s_pmpaddr[i]);
|
||||
for (i = 1U; i < PMP_REGION_NUM_FOR_STACK_GUARD; i++)
|
||||
csr_write_enum(CSR_PMPADDR0 + i, thread->arch.s_pmpaddr[i]);
|
||||
|
||||
for (i = 0U; i < PMP_CFG_CSR_NUM_FOR_STACK_GUARD; i++)
|
||||
csr_write_enum(CSR_PMPCFG0 + i, thread->arch.s_pmpcfg[i]);
|
||||
|
|
@ -625,13 +808,13 @@ void z_riscv_configure_stack_guard(struct k_thread *thread)
|
|||
|
||||
void z_riscv_configure_interrupt_stack_guard(void)
|
||||
{
|
||||
if (PMP_GUARD_ALIGN_AND_SIZE > 4) {
|
||||
z_riscv_pmp_set(0, PMP_NAPOT | PMP_L,
|
||||
(ulong_t) z_interrupt_stacks[0] |
|
||||
TO_NAPOT_RANGE(PMP_GUARD_ALIGN_AND_SIZE));
|
||||
} else {
|
||||
z_riscv_pmp_set(0, PMP_NA4 | PMP_L,
|
||||
(ulong_t) z_interrupt_stacks[0]);
|
||||
int index = 0, ret;
|
||||
|
||||
LOG_DBG("Set static PMP region %d for IRQ stack guard", index);
|
||||
ret = riscv_pmp_region_set(index, &irq_stack_guard_region);
|
||||
if (ret == -EINVAL) {
|
||||
LOG_ERR("Configure static PMP region of IRQ stack guard "
|
||||
"failed");
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_PMP_STACK_GUARD */
|
||||
|
|
@ -640,6 +823,7 @@ void z_riscv_configure_interrupt_stack_guard(void)
|
|||
|
||||
void z_riscv_pmp_init_thread(struct k_thread *thread)
|
||||
{
|
||||
/* Clear [u|s]_pmp[cfg|addr] field of k_thread */
|
||||
unsigned char i;
|
||||
ulong_t *pmpcfg;
|
||||
|
||||
|
|
|
|||
|
|
@ -38,21 +38,6 @@
|
|||
|
||||
#ifdef CONFIG_RISCV_PMP
|
||||
|
||||
/*
|
||||
* @brief Set a Physical Memory Protection slot
|
||||
*
|
||||
* Configure a memory region to be secured by one of the 16 PMP entries.
|
||||
*
|
||||
* @param index Number of the targeted PMP entrie (0 to 15 only).
|
||||
* @param cfg_val Configuration value (cf datasheet or defined flags)
|
||||
* @param addr_val Address register value
|
||||
*
|
||||
* This function shall only be called from Secure state.
|
||||
*
|
||||
* @return -1 if bad argument, 0 otherwise.
|
||||
*/
|
||||
int z_riscv_pmp_set(unsigned int index, ulong_t cfg_val, ulong_t addr_val);
|
||||
|
||||
/*
|
||||
* @brief Reset to 0 all PMP setup registers
|
||||
*/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue