diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi index 7387f6af00b..bf04c700805 100644 --- a/dts/arm/st/g4/stm32g4.dtsi +++ b/dts/arm/st/g4/stm32g4.dtsi @@ -167,6 +167,22 @@ label = "LPUART_1"; }; + iwdg: watchdog@40003000 { + compatible = "st,stm32-watchdog"; + reg = <0x40003000 0x400>; + label = "IWDG"; + status = "disabled"; + }; + + wwdg: watchdog@40002c00 { + compatible = "st,stm32-window-watchdog"; + reg = <0x40002C00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; + label = "WWDG"; + interrupts = <0 7>; + status = "disabled"; + }; + i2c1: i2c@40005400 { compatible = "st,stm32-i2c-v2"; clock-frequency = ; diff --git a/soc/arm/st_stm32/stm32g4/dts_fixup.h b/soc/arm/st_stm32/stm32g4/dts_fixup.h index 6ff0a6284cb..97578511ad6 100644 --- a/soc/arm/st_stm32/stm32g4/dts_fixup.h +++ b/soc/arm/st_stm32/stm32g4/dts_fixup.h @@ -251,4 +251,13 @@ #define DT_TIM_STM32_17_CLOCK_BITS DT_ST_STM32_TIMERS_40014800_CLOCK_BITS #define DT_TIM_STM32_17_CLOCK_BUS DT_ST_STM32_TIMERS_40014800_CLOCK_BUS +#define DT_WDT_0_NAME DT_INST_0_ST_STM32_WATCHDOG_LABEL + +#define DT_WWDT_0_BASE_ADDRESS DT_INST_0_ST_STM32_WINDOW_WATCHDOG_BASE_ADDRESS +#define DT_WWDT_0_NAME DT_INST_0_ST_STM32_WINDOW_WATCHDOG_LABEL +#define DT_WWDT_0_IRQ DT_INST_0_ST_STM32_WINDOW_WATCHDOG_IRQ_0 +#define DT_WWDT_0_IRQ_PRI DT_INST_0_ST_STM32_WINDOW_WATCHDOG_IRQ_0_PRIORITY +#define DT_WWDT_0_CLOCK_BITS DT_INST_0_ST_STM32_WINDOW_WATCHDOG_CLOCK_BITS +#define DT_WWDT_0_CLOCK_BUS DT_INST_0_ST_STM32_WINDOW_WATCHDOG_CLOCK_BUS + /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32g4/soc.h b/soc/arm/st_stm32/stm32g4/soc.h index b4c68671596..eda3d015f74 100644 --- a/soc/arm/st_stm32/stm32g4/soc.h +++ b/soc/arm/st_stm32/stm32g4/soc.h @@ -60,6 +60,14 @@ #include #endif +#ifdef CONFIG_IWDG_STM32 +#include +#endif + +#ifdef CONFIG_WWDG_STM32 +#include +#endif + #ifdef CONFIG_ENTROPY_STM32_RNG #include #endif