drivers: ieee802154: kw41z: add support for KW40Z
Add support for KW40Z in the KW41Z IEEE 802.15.4 driver as both chips expose almost the same radio registers. Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
This commit is contained in:
parent
af98f0a806
commit
e392ef2285
1 changed files with 43 additions and 4 deletions
|
@ -31,6 +31,7 @@
|
|||
#define KW41Z_ACK_WAIT_TIME 54
|
||||
#define KW41Z_IDLE_WAIT_RETRIES 5
|
||||
#define KW41Z_PRE_RX_WAIT_TIME 1
|
||||
#define KW40Z_POST_SEQ_WAIT_TIME 1
|
||||
|
||||
#define RADIO_0_IRQ_PRIO 0x80
|
||||
#define KW41Z_FCS_LENGTH 2
|
||||
|
@ -97,6 +98,16 @@ static inline u8_t kw41z_get_seq_state(void)
|
|||
|
||||
static inline void kw41z_set_seq_state(u8_t state)
|
||||
{
|
||||
#if CONFIG_SOC_MKW40Z4
|
||||
/*
|
||||
* KW40Z seems to require a small delay when switching to IDLE state
|
||||
* after a programmed sequence is complete.
|
||||
*/
|
||||
if (state == KW41Z_STATE_IDLE) {
|
||||
k_busy_wait(KW40Z_POST_SEQ_WAIT_TIME);
|
||||
}
|
||||
#endif
|
||||
|
||||
ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_XCVSEQ_MASK) |
|
||||
ZLL_PHY_CTRL_XCVSEQ(state);
|
||||
}
|
||||
|
@ -294,8 +305,7 @@ static inline void kw41z_rx(struct kw41z_context *kw41z, u8_t len)
|
|||
{
|
||||
struct net_pkt *pkt = NULL;
|
||||
struct net_buf *frag = NULL;
|
||||
u16_t reg_val = 0;
|
||||
u8_t pkt_len, hw_lqi, i;
|
||||
u8_t pkt_len, hw_lqi;
|
||||
|
||||
pkt_len = len - KW41Z_FCS_LENGTH;
|
||||
|
||||
|
@ -313,8 +323,9 @@ static inline void kw41z_rx(struct kw41z_context *kw41z, u8_t len)
|
|||
|
||||
net_pkt_frag_insert(pkt, frag);
|
||||
|
||||
#if CONFIG_SOC_MKW41Z4
|
||||
/* PKT_BUFFER_RX needs to be accessed alligned to 16 bits */
|
||||
for (i = 0; i < pkt_len; i++) {
|
||||
for (u16_t reg_val = 0, i = 0; i < pkt_len; i++) {
|
||||
if (i % 2 == 0) {
|
||||
reg_val = ZLL->PKT_BUFFER_RX[i/2];
|
||||
frag->data[i] = reg_val & 0xFF;
|
||||
|
@ -322,6 +333,25 @@ static inline void kw41z_rx(struct kw41z_context *kw41z, u8_t len)
|
|||
frag->data[i] = reg_val >> 8;
|
||||
}
|
||||
}
|
||||
#else /* CONFIG_SOC_MKW40Z4 */
|
||||
/* PKT_BUFFER needs to be accessed alligned to 32 bits */
|
||||
for (u32_t reg_val = 0, i = 0; i < pkt_len; i++) {
|
||||
switch (i % 4) {
|
||||
case 0:
|
||||
reg_val = ZLL->PKT_BUFFER[i/4];
|
||||
frag->data[i] = reg_val & 0xFF;
|
||||
break;
|
||||
case 1:
|
||||
frag->data[i] = (reg_val >> 8) & 0xFF;
|
||||
break;
|
||||
case 2:
|
||||
frag->data[i] = (reg_val >> 16) & 0xFF;
|
||||
break;
|
||||
default:
|
||||
frag->data[i] = reg_val >> 24;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
net_buf_add(frag, pkt_len);
|
||||
|
||||
|
@ -364,8 +394,13 @@ static int kw41z_tx(struct device *dev, struct net_pkt *pkt,
|
|||
return 0;
|
||||
}
|
||||
|
||||
#if CONFIG_SOC_MKW41Z4
|
||||
((u8_t *)ZLL->PKT_BUFFER_TX)[0] = payload_len + KW41Z_FCS_LENGTH;
|
||||
memcpy(((u8_t *)ZLL->PKT_BUFFER_TX) + 1, payload, payload_len);
|
||||
#else /* CONFIG_SOC_MKW40Z4 */
|
||||
((u8_t *)ZLL->PKT_BUFFER)[0] = payload_len + KW41Z_FCS_LENGTH;
|
||||
memcpy(((u8_t *)ZLL->PKT_BUFFER) + 1, payload, payload_len);
|
||||
#endif
|
||||
|
||||
/* Set CCA mode */
|
||||
ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_CCATYPE_MASK) |
|
||||
|
@ -526,7 +561,6 @@ static int kw41z_init(struct device *dev)
|
|||
|
||||
/* Disable all timers, enable AUTOACK, mask all interrupts */
|
||||
ZLL->PHY_CTRL = ZLL_PHY_CTRL_CCATYPE(KW41Z_CCA_MODE1) |
|
||||
ZLL_IRQSTS_WAKE_IRQ_MASK |
|
||||
ZLL_PHY_CTRL_CRC_MSK_MASK |
|
||||
ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK |
|
||||
ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK |
|
||||
|
@ -534,6 +568,11 @@ static int kw41z_init(struct device *dev)
|
|||
ZLL_PHY_CTRL_RXMSK_MASK |
|
||||
ZLL_PHY_CTRL_TXMSK_MASK |
|
||||
ZLL_PHY_CTRL_SEQMSK_MASK;
|
||||
|
||||
#if CONFIG_SOC_MKW41Z4
|
||||
ZLL->PHY_CTRL |= ZLL_IRQSTS_WAKE_IRQ_MASK;
|
||||
#endif
|
||||
|
||||
#if KW41Z_AUTOACK_ENABLED
|
||||
ZLL->PHY_CTRL |= ZLL_PHY_CTRL_AUTOACK_MASK;
|
||||
#endif
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue