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soc: espressif: move code start prior hw init

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Make sure vector table and BSS clean up
is performed pior hardware initialization.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is contained in:
Sylvio Alves 2025-01-10 10:48:37 -03:00 • committed by Benjamin Cabé
commit e36d702acd
28 changed files with 273 additions and 540 deletions
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7
soc/espressif/esp32c6/hw_init.c
View file

@ -75,13 +75,6 @@ int hardware_init(void)
print_banner();
#endif /* CONFIG_ESP_CONSOLE */
spi_flash_init_chip_state();
err = esp_flash_init_default_chip();
if (err != 0) {
ESP_EARLY_LOGE(TAG, "Failed to init flash chip, error %d", err);
return err;
}
cache_hal_init();
mmu_hal_init();

70
soc/espressif/esp32c6/soc.c
View file

@ -1,73 +1,39 @@
/*
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
* Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Include esp-idf headers first to avoid redefining BIT() macro */
#include <soc/timer_group_reg.h>
#include <soc/ext_mem_defs.h>
#include <soc/gpio_reg.h>
#include <soc/system_reg.h>
#include "hal/wdt_hal.h"
#include "esp_cpu.h"
#include "hal/soc_hal.h"
#include "hal/cpu_hal.h"
#include "esp_timer.h"
#include "esp_private/system_internal.h"
#include "esp_clk_internal.h"
#include <soc/interrupt_reg.h>
#include <esp_private/spi_flash_os.h>
#include "esp_private/esp_mmu_map_private.h"
#include <esp_flash_internal.h>
#include <soc.h>
#include <soc_init.h>
#include <flash_init.h>
#include <esp_private/cache_utils.h>
#include <esp_private/system_internal.h>
#include <esp_timer.h>
#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
#include <zephyr/kernel_structs.h>
#include <kernel_internal.h>
#include <string.h>
#include <zephyr/toolchain/gcc.h>
#include <soc.h>
/*
* This is written in C rather than assembly since, during the port bring up,
* Zephyr is being booted by the Espressif bootloader. With it, the C stack
* is already set up.
*/
void IRAM_ATTR __esp_platform_start(void)
extern void esp_reset_reason_init(void);
void IRAM_ATTR __esp_platform_app_start(void)
{
__asm__ __volatile__("la t0, _esp32c6_vector_table\n"
"csrw mtvec, t0\n");
z_bss_zero();
/* Disable normal interrupts. */
csr_read_clear(mstatus, MSTATUS_MIE);
esp_reset_reason_init();
#ifndef CONFIG_MCUBOOT
/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
* related issues in application. Hence disable that as we are about to start
* Zephyr environment.
*/
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
wdt_hal_disable(&rtc_wdt_ctx);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
esp_timer_early_init();
esp_mspi_pin_init();
esp_flash_config();
esp_flash_app_init();
esp_intr_initialize();
esp_mmu_map_init();
/* Start Zephyr */
z_cstart();
#endif /* !CONFIG_MCUBOOT */
CODE_UNREACHABLE;
}
/*Initialize the esp32c6 interrupt controller */
void IRAM_ATTR __esp_platform_mcuboot_start(void)
{
esp_intr_initialize();
/* Start Zephyr */

3
soc/espressif/esp32c6/soc.h
View file

@ -27,7 +27,8 @@
#ifndef _ASMLANGUAGE
void __esp_platform_start(void);
void __esp_platform_mcuboot_start(void);
void __esp_platform_app_start(void);
static inline uint32_t esp_core_id(void)
{

6
soc/espressif/esp32c6/vectors.S
View file

@ -22,12 +22,12 @@ GTEXT(_isr_wrapper)
* only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
*/
.global _esp32c6_vector_table
.global _esp_vector_table
.section .exception_vectors.text
.balign 0x100
.type _esp32c6_vector_table, @function
.type _esp_vector_table, @function
_esp32c6_vector_table:
_esp_vector_table:
.option push
.option norvc
.rept (32)