michaelh/zephyr
1
0
Fork 0
Code Releases Activity

x86: implement kernel page table isolation

Browse source 
Implement a set of per-cpu trampoline stacks which all
interrupts and exceptions will initially land on, and also
as an intermediate stack for privilege changes as we need
some stack space to swap page tables.

Set up the special trampoline page which contains all the
trampoline stacks, TSS, and GDT. This page needs to be
present in the user page tables or interrupts don't work.

CPU exceptions, with KPTI turned on, are treated as interrupts
and not traps so that we have IRQs locked on exception entry.

Add some additional macros for defining IDT entries.

Add special handling of locore text/rodata sections when
creating user mode page tables on x86-64.

Restore qemu_x86_64 to use KPTI, and remove restrictions on
enabling user mode on x86-64.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2019-12-18 23:57:25 -08:00 • committed by Anas Nashif
commit e34f1cee06
12 changed files with 493 additions and 139 deletions
Download patch file Download diff file Expand all files Collapse all files

1
arch/x86/core/intel64/thread.c
View file

@ -7,6 +7,7 @@
#include <ksched.h>
#include <kernel_structs.h>
#include <kernel_internal.h>
#include <offsets_short.h>
extern void x86_sse_init(struct k_thread *); /* in locore.S */