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x86: intel64: enable no-execute

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Set the NXE bit in the EFER MSR so that the NX bit can
be set in page tables. Otherwise, the NX bit is treated
as reserved and leads to a fault if set.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2019-10-10 11:47:57 -07:00 • committed by Andrew Boie
commit e340f8d22e
2 changed files with 3 additions and 2 deletions
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4
arch/x86/core/intel64/locore.S
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@ -112,9 +112,9 @@ go64: movl %cr4, %eax /* enable PAE and SSE */
movl $pml4, %eax /* load page base */
movl %eax, %cr3
movl $X86_EFER_MSR, %ecx /* enable long mode */
movl $X86_EFER_MSR, %ecx /* enable long mode and no-execute */
rdmsr
orl $X86_EFER_MSR_LME, %eax
orl $(X86_EFER_MSR_LME | X86_EFER_MSR_NXE), %eax
wrmsr
movl %cr0, %eax /* enable paging */

1
include/arch/x86/msr.h
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@ -26,6 +26,7 @@
#define X86_EFER_MSR 0xC0000080
#define X86_EFER_MSR_LME BIT(8)
#define X86_EFER_MSR_NXE BIT(11)
#ifndef _ASMLANGUAGE
#ifdef __cplusplus