nios2: add base exception handling code
Change-Id: I56b0ec1a3576a77ca7bd6f2c0217de8053406927 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie
Inaky Perez-Gonzalez
parent
b6d9c5ca80
commit
e2ff2fdd91
5 changed files with 420 additions and 24 deletions
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@ -3,7 +3,7 @@ ccflags-y +=-I$(srctree)/arch/$(ARCH)/include
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ccflags-y += -I$(srctree)/kernel/microkernel/include
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obj-y += reset.o irq_manage.o fatal.o swap.o thread.o \
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cpu_idle.o irq_offload.o prep_c.o crt0.o
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cpu_idle.o irq_offload.o prep_c.o crt0.o \
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exception.o
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obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
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244
arch/nios2/core/exception.S
Normal file
244
arch/nios2/core/exception.S
Normal file
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@ -0,0 +1,244 @@
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/*
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* Copyright (c) 2016 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define _ASMLANGUAGE
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#include <arch/nios2/asm.h>
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#include <nano_private.h>
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/* exports */
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GTEXT(_exception)
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GTEXT(_exception_exit)
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GTEXT(_exception_enter_fault)
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/* import */
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GTEXT(_Fault)
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GTEXT(_Swap)
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GTEXT(_exception_try_muldiv)
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/* Allows use of r1/at register, otherwise reserved for assembler use */
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.set noat
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/* Placed into special 'exception' section so that the linker can put this code
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* at ALT_CPU_EXCEPTION_ADDR defined in system.h
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*
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* This is the common entry point for processor exceptions and interrupts from
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* the Internal Interrupt Controller (IIC).
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*
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* If the External (EIC) controller is in use, then we will never get here on
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* behalf of an interrupt, instead the EIC driver will have set up a vector
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* table and the processor will jump directly into the appropriate table
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* entry.
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*/
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SECTION_FUNC(exception.entry, _exception)
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/* Reserve thread stack space for saving context */
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addi sp, sp, -76
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/* Preserve all caller-saved registers onto the thread's stack */
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stw ra, 0(sp)
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/* Gap here for muldiv handler to store zero register */
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stw r1, 8(sp)
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stw r2, 12(sp)
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stw r3, 16(sp)
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stw r4, 20(sp)
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stw r5, 24(sp)
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stw r6, 28(sp)
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stw r7, 32(sp)
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stw r8, 36(sp)
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stw r9, 40(sp)
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stw r10, 44(sp)
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stw r11, 48(sp)
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stw r12, 52(sp)
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stw r13, 56(sp)
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stw r14, 60(sp)
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stw r15, 64(sp)
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/* Store value of estatus control register */
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rdctl et, estatus
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stw et, 68(sp)
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/* ea-4 is the address of the instruction when the exception happened,
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* put this in the stack frame as well
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*/
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addi r15, ea, -4
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stw r15, 72(sp)
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/* Figure out whether we are here because of an interrupt or an
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* exception. If an interrupt, switch stacks and enter IRQ handling
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* code. If an exception, remain on current stack and enter exception
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* handing code. From the CPU manual, ipending must be nonzero and
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* estatis.PIE must be enabled for this to be considered an interrupt.
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*
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* Stick ipending in r4 since it will be an arg for _enter_irq
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*/
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rdctl r4, ipending
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beq r4, zero, not_interrupt
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/* We stashed estatus in et earlier */
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andi r15, et, 1
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beq r15, zero, not_interrupt
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/* If we get here, this is an interrupt */
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/* Grab a reference to _nanokernel in r10 so we can determine the
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* current irq stack pointer
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*/
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movhi r10, %hi(_nanokernel)
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ori r10, r10, %lo(_nanokernel)
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/* Stash a copy of thread's sp in r12 so that we can put it on the IRQ
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* stack
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*/
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mov r12, sp
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/* Switch to interrupt stack */
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ldw sp, __tNANO_irq_sp_OFFSET(r10)
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/* Store thread stack pointer onto IRQ stack */
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addi sp, sp, -4
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stw r12, 0(sp)
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BRANCH_LABEL(on_irq_stack)
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#if 0 /* TODO enable interrupt handling code */
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/* Enter C interrupt handling code. Value of ipending will be the
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* function parameter since we put it in r4
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*/
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call _enter_irq
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#endif
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/* Interrupt handler finished and the interrupt should be serviced
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* now, the appropriate bits in ipending should be cleared */
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/* Get a reference to _nanokernel again in r10 */
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movhi r10, %hi(_nanokernel)
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ori r10, r10, %lo(_nanokernel)
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/* Determine whether the execution of the ISR requires a context
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* switch. If the interrupted thread is PREEMPTIBLE (a task) and
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* _nanokernel.fiber is non-NULL, a _Swap() needs to occur.
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*/
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/* Check (_nanokernel.current->flags & PREEMPTIBLE), if not
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* goto no_reschedule
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*/
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ldw r11, __tNANO_current_OFFSET(r10)
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ldw r12, __tTCS_flags_OFFSET(r11)
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movi r13, PREEMPTIBLE
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and r12, r13, r12
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beq r12, zero, no_reschedule
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/* Check _nanokernel.fiber != NULL, if NULL goto no_reschedule */
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ldw r11, __tNANO_fiber_OFFSET(r10)
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beq r11, zero, no_reschedule
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/*
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* A context reschedule is required: keep the volatile registers of
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* the interrupted thread on the context's stack. Utilize
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* the existing _Swap() primitive to save the remaining
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* thread's registers (including floating point) and perform
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* a switch to the new thread.
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*/
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/* We put the thread stack pointer on top of the IRQ stack before
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* we switched stacks. Restore it to go back to thread stack
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*/
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ldw sp, 0(sp)
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/* Argument to Swap() is estatus since that's the state of the
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* status register before the exception happened. When coming
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* out of the context switch we need this info to restore
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* IRQ lock state. We put this value in et earlier.
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*/
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mov r4, et
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call _Swap
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jmpi _exception_exit
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BRANCH_LABEL(not_interrupt)
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#if 0 /* TODO enable multiply / divide exception handing */
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/* Since this wasn't an interrupt we're not going to restart the
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* faulting instruction. If it's an unimplemented math instruction,
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* the muldiv code will handle it, else we just give up and _Fault.
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*
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* We earlier put ea - 4 in the stack frame, replace it with just ea
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*/
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stw ea, 72(sp)
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/* Could be an unimplemented instruction we have to emulate.
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* Smaller Nios II cores don't have multiply or divide instructions.
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* This code comes back to either _exception_enter_fault or
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* _exception_exit
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*/
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jmpi _exception_try_muldiv
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#endif
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SECTION_FUNC(exception.entry, _exception_enter_fault)
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/* If we get here, the exception wasn't in interrupt or an
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* unimplemented math instruction. Let _Fault() handle it in
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* C domain
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*/
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ldw r4, 0(sp)
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call _Fault
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jmpi _exception_exit
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BRANCH_LABEL(no_reschedule)
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/* We put the thread stack pointer on top of the IRQ stack before
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* we switched stacks. Restore it to go back to thread stack
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*/
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ldw sp, 0(sp)
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/* Fall through */
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SECTION_FUNC(exception.entry, _exception_exit)
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/* We are on the thread stack. Restore all saved registers
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* and return to the interrupted context */
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/* Return address from the exception */
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ldw ea, 72(sp)
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/* Restore estatus
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* XXX is this right??? */
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ldw r5, 68(sp)
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wrctl estatus, r5
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/* Restore caller-saved registers */
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ldw ra, 0(sp)
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ldw r1, 8(sp)
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ldw r2, 12(sp)
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ldw r3, 16(sp)
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ldw r4, 20(sp)
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ldw r5, 24(sp)
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ldw r6, 28(sp)
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ldw r7, 32(sp)
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ldw r8, 36(sp)
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ldw r9, 40(sp)
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ldw r10, 44(sp)
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ldw r11, 48(sp)
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ldw r12, 52(sp)
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ldw r13, 56(sp)
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ldw r14, 60(sp)
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ldw r15, 64(sp)
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/* Put the stack pointer back where it was when we entered
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* exception state
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*/
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addi sp, sp, 76
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/* All done, copy estatus into status and transfer to ea */
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eret
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@ -19,9 +19,26 @@
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#include <nano_private.h>
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#include <misc/printk.h>
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/* TODO initialize with sentinel values */
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const NANO_ESF _default_esf;
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const NANO_ESF _default_esf = {
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad,
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0xdeadbaad
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};
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/**
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*
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@ -42,22 +59,73 @@ const NANO_ESF _default_esf;
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FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
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const NANO_ESF *esf)
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{
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/* STUB TODO: dump out reason for the error and any interesting
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* info in esf
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*/
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#ifdef CONFIG_PRINTK
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switch (reason) {
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case _NANO_ERR_CPU_EXCEPTION:
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case _NANO_ERR_SPURIOUS_INT:
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break;
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case _NANO_ERR_INVALID_TASK_EXIT:
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printk("***** Invalid Exit Software Error! *****\n");
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break;
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case _NANO_ERR_ALLOCATION_FAIL:
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printk("**** Kernel Allocation Failure! ****\n");
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break;
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default:
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printk("**** Unknown Fatal Error %d! ****\n", reason);
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break;
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}
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printk("Current thread ID: 0x%x\n"
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"Faulting instruction: 0x%x\n"
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" r1: 0x%x r2: 0x%x r3: 0x%x r4: 0x%x\n"
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" r5: 0x%x r6: 0x%x r7: 0x%x r8: 0x%x\n"
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" r9: 0x%x r10: 0x%x r11: 0x%x r12: 0x%x\n"
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"r13: 0x%x r14: 0x%x r15: 0x%x ra: 0x%x\n"
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"estatus: %x\n", sys_thread_self_get(), esf->instr,
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esf->r1, esf->r2, esf->r3, esf->r4,
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esf->r5, esf->r6, esf->r7, esf->r8,
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esf->r9, esf->r10, esf->r11, esf->r12,
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esf->r13, esf->r14, esf->r15, esf->ra,
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esf->estatus);
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#endif
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_SysFatalErrorHandler(reason, esf);
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}
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FUNC_NORETURN void _Fault(void)
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FUNC_NORETURN void _Fault(const NANO_ESF *esf)
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{
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/* STUB TODO dump out reason for this exception */
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#ifdef CONFIG_PRINTK
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/* Unfortunately, completely unavailable on Nios II/e cores */
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#ifdef NIOS2_HAS_EXTRA_EXCEPTION_INFO
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uint32_t exc_reg, badaddr_reg, eccftl;
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enum nios2_exception_cause cause;
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_NanoFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, &_default_esf);
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exc_reg = _nios2_creg_read(NIOS2_CR_EXCEPTION);
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/* Bit 31 indicates potentially fatal ECC error */
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eccftl = (exc_reg & NIOS2_EXCEPTION_REG_ECCFTL_MASK) != 0;
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/* Bits 2-6 contain the cause code */
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cause = (exc_reg & NIOS2_EXCEPTION_REG_CAUSE_MASK)
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>> NIOS2_EXCEPTION_REG_CAUSE_OFST;
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printk("Exception cause: 0x%x ECCFTL: %d\n", exc_reg, eccftl);
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if (BIT(cause) & NIOS2_BADADDR_CAUSE_MASK) {
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badaddr_reg = _nios2_creg_read(NIOS2_CR_BADADDR);
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printk("Badaddr: 0x%x\n", badaddr_reg);
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}
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#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */
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#endif /* CONFIG_PRINTK */
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_NanoFatalErrorHandler(_NANO_ERR_CPU_EXCEPTION, esf);
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}
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/**
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*
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* @brief Fatal error handler
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@ -74,20 +142,42 @@ FUNC_NORETURN void _Fault(void)
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* information to a persistent repository and/or rebooting the system.
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*
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* @param reason the fatal error reason
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* @param pEsf the pointer to the exception stack frame
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* @param pEsf pointer to exception stack frame
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*
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* @return This function does not return.
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* @return N/A
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*/
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FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
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const NANO_ESF *esf)
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const NANO_ESF *pEsf)
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{
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/* STUB TODO try to abort task/fibers like in the x86 implementation */
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printk("Fatal error!\n");
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nano_context_type_t curCtx = sys_execution_context_type_get();
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while (1) {
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/* whee! */
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ARG_UNUSED(reason);
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ARG_UNUSED(pEsf);
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if ((curCtx != NANO_CTX_ISR) && !_is_thread_essential()) {
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#ifdef CONFIG_MICROKERNEL
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if (curCtx == NANO_CTX_TASK) {
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extern FUNC_NORETURN void _TaskAbort(void);
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printk("Fatal task error! Aborting task.\n");
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_TaskAbort();
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} else
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#endif /* CONFIG_MICROKERNEL */
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{
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printk("Fatal fiber error! Aborting fiber.\n");
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fiber_abort();
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}
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CODE_UNREACHABLE;
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}
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printk("Fatal fault in %s ! Spinning...\n",
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curCtx == NANO_CTX_ISR
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? "ISR"
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: curCtx == NANO_CTX_FIBER ? "essential fiber"
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: "essential task");
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#ifdef NIOS2_HAS_DEBUG_STUB
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_nios2_break();
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#endif
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for (;;)
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; /* Spin forever */
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}
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@ -154,6 +154,7 @@ struct s_NANO {
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typedef struct s_NANO tNANO;
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extern tNANO _nanokernel;
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extern char _interrupt_stack[CONFIG_ISR_STACK_SIZE];
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/* Arch-specific nanokernel APIs */
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@ -162,7 +163,8 @@ void nano_cpu_atomic_idle(unsigned int key);
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static ALWAYS_INLINE void nanoArchInit(void)
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{
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/* STUB */
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_nanokernel.irq_sp = (char *)STACK_ROUND_DOWN(_interrupt_stack +
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CONFIG_ISR_STACK_SIZE);
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}
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static ALWAYS_INLINE void fiberRtnValueSet(struct tcs *fiber,
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@ -34,10 +34,11 @@ extern "C" {
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#define STACK_ALIGN 4
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#define _NANO_ERR_HW_EXCEPTION (0) /* MPU/Bus/Usage fault */
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#define _NANO_ERR_CPU_EXCEPTION (0) /* Any unhandled exception */
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#define _NANO_ERR_INVALID_TASK_EXIT (1) /* Invalid task exit */
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#define _NANO_ERR_STACK_CHK_FAIL (2) /* Stack corruption detected */
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#define _NANO_ERR_ALLOCATION_FAIL (3) /* Kernel Allocation Failure */
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#define _NANO_ERR_SPURIOUS_INT (4) /* Spurious interrupt */
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#ifndef _ASMLANGUAGE
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#include <stdint.h>
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@ -93,8 +94,25 @@ void _arch_irq_enable(unsigned int irq);
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void _arch_irq_disable(unsigned int irq);
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struct __esf {
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/* XXX - not defined yet */
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uint32_t placeholder;
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uint32_t ra; /* return address r31 */
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uint32_t r0; /* zero register */
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uint32_t r1; /* at */
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uint32_t r2; /* return value */
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uint32_t r3; /* return value */
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uint32_t r4; /* register args */
|
||||
uint32_t r5; /* register args */
|
||||
uint32_t r6; /* register args */
|
||||
uint32_t r7; /* register args */
|
||||
uint32_t r8; /* Caller-saved general purpose */
|
||||
uint32_t r9; /* Caller-saved general purpose */
|
||||
uint32_t r10; /* Caller-saved general purpose */
|
||||
uint32_t r11; /* Caller-saved general purpose */
|
||||
uint32_t r12; /* Caller-saved general purpose */
|
||||
uint32_t r13; /* Caller-saved general purpose */
|
||||
uint32_t r14; /* Caller-saved general purpose */
|
||||
uint32_t r15; /* Caller-saved general purpose */
|
||||
uint32_t estatus;
|
||||
uint32_t instr; /* Instruction being executed when exc occurred */
|
||||
};
|
||||
|
||||
typedef struct __esf NANO_ESF;
|
||||
|
|
@ -103,6 +121,48 @@ extern const NANO_ESF _default_esf;
|
|||
FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
|
||||
const NANO_ESF *esf);
|
||||
|
||||
|
||||
enum nios2_exception_cause {
|
||||
NIOS2_EXCEPTION_UNKNOWN = -1,
|
||||
NIOS2_EXCEPTION_RESET = 0,
|
||||
NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST = 1,
|
||||
NIOS2_EXCEPTION_INTERRUPT = 2,
|
||||
NIOS2_EXCEPTION_TRAP_INST = 3,
|
||||
NIOS2_EXCEPTION_UNIMPLEMENTED_INST = 4,
|
||||
NIOS2_EXCEPTION_ILLEGAL_INST = 5,
|
||||
NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR = 6,
|
||||
NIOS2_EXCEPTION_MISALIGNED_TARGET_PC = 7,
|
||||
NIOS2_EXCEPTION_DIVISION_ERROR = 8,
|
||||
NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR = 9,
|
||||
NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST = 10,
|
||||
NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR = 11,
|
||||
NIOS2_EXCEPTION_TLB_MISS = 12,
|
||||
NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION = 13,
|
||||
NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION = 14,
|
||||
NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION = 15,
|
||||
NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION = 16,
|
||||
NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION = 17,
|
||||
NIOS2_EXCEPTION_ECC_TLB_ERR = 18,
|
||||
NIOS2_EXCEPTION_ECC_FETCH_ERR = 19,
|
||||
NIOS2_EXCEPTION_ECC_REGISTER_FILE_ERR = 20,
|
||||
NIOS2_EXCEPTION_ECC_DATA_ERR = 21,
|
||||
NIOS2_EXCEPTION_ECC_DATA_CACHE_WRITEBACK_ERR = 22
|
||||
};
|
||||
|
||||
/* Bitfield indicating which exception cause codes report a valid
|
||||
* badaddr register. NIOS2_EXCEPTION_TLB_MISS and NIOS2_EXCEPTION_ECC_TLB_ERR
|
||||
* are deliberately not included here, you need to check if TLBMISC.D=1
|
||||
*/
|
||||
#define NIOS2_BADADDR_CAUSE_MASK \
|
||||
(BIT(NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR) | \
|
||||
BIT(NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR) | \
|
||||
BIT(NIOS2_EXCEPTION_MISALIGNED_TARGET_PC) | \
|
||||
BIT(NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION) | \
|
||||
BIT(NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION) | \
|
||||
BIT(NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION) | \
|
||||
BIT(NIOS2_EXCEPTION_ECC_DATA_ERR))
|
||||
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue