From e282b0ea8424a6ada37632bcea0646a7c069ec42 Mon Sep 17 00:00:00 2001 From: Lucas Tamborrino Date: Thu, 2 May 2024 16:39:17 -0300 Subject: [PATCH] soc: esp32xx: refactor clock and RTC subsystems The RTC subsystem in espressif's SOCs, among other tasks is responsible for clock selection for CPU and for low power domain clocks such as RTC_SLOW and RTC_FAST. This commit allows for proper clock source and rate selection for CPU, using the espressif,riscv and espressif,xtensa-lx6/7 bindings. It also enables clock selection for RTC_FAST and RTC_SLOW, that impacts some peripherals, such as rtc_timer. Signed-off-by: Lucas Tamborrino --- .../esp32_devkitc_wroom_appcpu.dts | 8 - .../esp32_devkitc_wroom_procpu.dts | 9 - .../esp32_devkitc_wrover_appcpu.dts | 8 - .../esp32_devkitc_wrover_procpu.dts | 8 - .../esp32_ethernet_kit_appcpu.dts | 8 - .../esp32_ethernet_kit_procpu.dts | 8 - .../esp32c3_devkitm/esp32c3_devkitm.dts | 6 +- .../esp32s2_devkitc/esp32s2_devkitc.dts | 4 - .../espressif/esp32s2_saola/esp32s2_saola.dts | 4 - .../esp32s3_devkitc_appcpu.dts | 8 - .../esp32s3_devkitc_procpu.dts | 8 - .../esp32s3_devkitm_appcpu.dts | 8 - .../esp32s3_devkitm_procpu.dts | 8 - .../esp_wrover_kit/esp_wrover_kit_appcpu.dts | 8 - .../esp_wrover_kit/esp_wrover_kit_procpu.dts | 8 - .../esp32s2_franzininho.dts | 4 - .../hardkernel/odroid_go/odroid_go_appcpu.dts | 8 - .../hardkernel/odroid_go/odroid_go_procpu.dts | 8 - .../heltec_wifi_lora32_v2_appcpu.dts | 8 - .../heltec_wifi_lora32_v2_procpu.dts | 8 - .../heltec_wireless_stick_lite_v3_appcpu.dts | 8 - .../heltec_wireless_stick_lite_v3_procpu.dts | 8 - .../kincony_kc868_a32_appcpu.dts | 8 - .../kincony_kc868_a32_procpu.dts | 9 - .../esp32c3_luatos_core.dtsi | 4 - .../esp32s3_luatos_core.dtsi | 8 - .../esp32s3_luatos_core_appcpu.dts | 8 - .../esp32s3_luatos_core_appcpu_usb.dts | 8 - .../m5stack_atom_lite_appcpu.dts | 8 - .../m5stack_atom_lite_procpu.dts | 8 - .../m5stack_atoms3/m5stack_atoms3_appcpu.dts | 8 - .../m5stack_atoms3/m5stack_atoms3_procpu.dts | 8 - .../m5stack_atoms3_lite_appcpu.dts | 8 - .../m5stack_atoms3_lite_procpu.dts | 8 - .../m5stack_core2/m5stack_core2_appcpu.dts | 8 - .../m5stack_core2/m5stack_core2_procpu.dts | 8 - .../m5stack_stamps3_appcpu.dts | 8 - .../m5stack_stamps3_procpu.dts | 8 - .../m5stickc_plus/m5stickc_plus_appcpu.dts | 8 - .../m5stickc_plus/m5stickc_plus_procpu.dts | 8 - boards/m5stack/stamp_c3/stamp_c3.dts | 4 - .../olimex_esp32_evb_appcpu.dts | 8 - .../olimex_esp32_evb_procpu.dts | 8 - boards/others/icev_wireless/icev_wireless.dts | 4 - boards/seeed/xiao_esp32c3/xiao_esp32c3.dts | 4 - .../xiao_esp32s3/xiao_esp32s3_appcpu.dts | 8 - .../xiao_esp32s3/xiao_esp32s3_procpu.dts | 8 - boards/vcc-gnd/yd_esp32/yd_esp32_appcpu.dts | 8 - boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts | 9 - .../esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts | 8 - .../esp32s3_touch_lcd_1_28_esp32s3_procpu.dts | 8 - .../esp32s2_lolin_mini/esp32s2_lolin_mini.dts | 5 - drivers/clock_control/clock_control_esp32.c | 352 ++++++++++++------ drivers/counter/Kconfig.esp32_tmr | 8 + drivers/counter/counter_esp32_rtc.c | 70 ++-- drivers/timer/esp32_sys_timer.c | 2 +- dts/bindings/clock/espressif,esp32-rtc.yaml | 26 +- .../counter/espressif,esp32-rtc-timer.yaml | 7 - dts/bindings/cpu/espressif,riscv.yaml | 21 +- dts/bindings/cpu/espressif,xtensa-lx6.yaml | 34 ++ dts/bindings/cpu/espressif,xtensa-lx7.yaml | 34 ++ .../espressif/esp32c3/esp32c3_common.dtsi | 22 +- dts/xtensa/espressif/esp32/esp32_common.dtsi | 30 +- .../espressif/esp32s2/esp32s2_common.dtsi | 25 +- .../espressif/esp32s3/esp32s3_common.dtsi | 30 +- .../clock_control/esp32_clock_control.h | 40 ++ .../zephyr/dt-bindings/clock/esp32_clock.h | 49 +-- .../zephyr/dt-bindings/clock/esp32c3_clock.h | 42 ++- .../zephyr/dt-bindings/clock/esp32s2_clock.h | 45 ++- .../zephyr/dt-bindings/clock/esp32s3_clock.h | 45 ++- soc/espressif/Kconfig | 22 +- soc/espressif/esp32/Kconfig.rtc | 94 ----- soc/espressif/esp32/soc.c | 7 - soc/espressif/esp32c3/Kconfig.rtc | 67 ---- soc/espressif/esp32c3/soc.c | 5 - soc/espressif/esp32s2/Kconfig.rtc | 93 ----- soc/espressif/esp32s2/soc.c | 4 - soc/espressif/esp32s3/Kconfig.rtc | 63 ---- soc/espressif/esp32s3/soc.c | 2 - 79 files changed, 629 insertions(+), 996 deletions(-) create mode 100644 dts/bindings/cpu/espressif,xtensa-lx6.yaml create mode 100644 dts/bindings/cpu/espressif,xtensa-lx7.yaml create mode 100644 include/zephyr/drivers/clock_control/esp32_clock_control.h delete mode 100644 soc/espressif/esp32/Kconfig.rtc delete mode 100644 soc/espressif/esp32c3/Kconfig.rtc delete mode 100644 soc/espressif/esp32s2/Kconfig.rtc delete mode 100644 soc/espressif/esp32s3/Kconfig.rtc diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts index c52b029ea55..ae7a2e1e7f6 100644 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts index 1708a7badf9..6ba26177f52 100644 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts @@ -39,15 +39,6 @@ }; }; -&cpu0 { - clock-frequency = ; - cpu-power-states = <&light_sleep &deep_sleep>; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts index 7298148a2c3..42c30a1079c 100644 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts index 60a063bc875..8d414b1e890 100644 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts @@ -39,14 +39,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu.dts b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu.dts index c5e1217b25c..eb613c2cc06 100644 --- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu.dts +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts index 7e8310c9605..7c6c32970b7 100644 --- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts @@ -26,14 +26,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts index f1d9481a8b7..039e72b4893 100644 --- a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts @@ -11,7 +11,7 @@ #include / { - model = "Espressif ESP32-DevkitM"; + model = "Espressif ESP32C3-DevkitM"; compatible = "espressif,esp32c3"; chosen { @@ -38,10 +38,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts index f8282767d22..f2c9d8cd3c9 100644 --- a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts +++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts @@ -39,10 +39,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/espressif/esp32s2_saola/esp32s2_saola.dts b/boards/espressif/esp32s2_saola/esp32s2_saola.dts index f7e73bb8f27..b204efab94b 100644 --- a/boards/espressif/esp32s2_saola/esp32s2_saola.dts +++ b/boards/espressif/esp32s2_saola/esp32s2_saola.dts @@ -39,10 +39,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu.dts b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu.dts index 5e5a1e2be48..886aae05270 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu.dts +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts index 4538c41fa5f..8894649a1bc 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts @@ -42,14 +42,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &usb_serial { status = "disabled"; }; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts index 3815ebdacf9..8a259eb99be 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts index 0cb8b962829..3ee4131ab33 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts @@ -42,14 +42,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &usb_serial { status = "okay"; }; diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu.dts b/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu.dts index f0a046705ee..ee3321726f2 100644 --- a/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu.dts +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts index ac0bacd604c..ad900df0e46 100644 --- a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts @@ -94,14 +94,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts index d8a6f1c7070..74d5f7610a9 100644 --- a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts +++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts @@ -43,10 +43,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/hardkernel/odroid_go/odroid_go_appcpu.dts b/boards/hardkernel/odroid_go/odroid_go_appcpu.dts index 6b59353de6d..1733da93f74 100644 --- a/boards/hardkernel/odroid_go/odroid_go_appcpu.dts +++ b/boards/hardkernel/odroid_go/odroid_go_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/hardkernel/odroid_go/odroid_go_procpu.dts b/boards/hardkernel/odroid_go/odroid_go_procpu.dts index c17c25823e2..0d150d08f16 100644 --- a/boards/hardkernel/odroid_go/odroid_go_procpu.dts +++ b/boards/hardkernel/odroid_go/odroid_go_procpu.dts @@ -99,14 +99,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu.dts b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu.dts index 4cf9e26b89d..1b9f7dff700 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu.dts +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts index 5e1c8c6c6ff..5fdec28fe33 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts @@ -58,14 +58,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu.dts b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu.dts index 6c49e64e8d1..92bde107bc3 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu.dts +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts index 255fc34c051..ca455d9d780 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts @@ -75,14 +75,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &adc1 { status ="okay"; }; diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.dts b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.dts index 7940256ff29..4717ca7fa62 100644 --- a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.dts +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.dts b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.dts index 0f459d7f7c5..5b60336d1bb 100644 --- a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.dts +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.dts @@ -26,15 +26,6 @@ }; }; -&cpu0 { - clock-frequency = ; - cpu-power-states = <&light_sleep &deep_sleep>; -}; - -&cpu1 { - clock-frequency = ; -}; - &gpio0 { status = "okay"; }; diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi index bf83c33898c..904668716f6 100644 --- a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi @@ -43,10 +43,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi index 849dd35bd67..883280c7b31 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi @@ -31,14 +31,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.dts index e33c7f43401..510e587925e 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.dts +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.dts index 7a251b40e04..b36963af013 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.dts +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu.dts b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu.dts index 59a908a3fef..f5db6e76116 100644 --- a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu.dts +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts index 53f6175e4d1..e4fae9d2543 100644 --- a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts @@ -53,14 +53,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu.dts b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu.dts index 91bcff6c007..a117ee02922 100644 --- a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu.dts +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts index 1b5a5da32da..aa80e0b8356 100644 --- a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts @@ -50,14 +50,6 @@ }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &usb_serial { status = "okay"; }; diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu.dts b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu.dts index 994c9b9a3b2..2323548e7fc 100644 --- a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu.dts +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts index 430de46a554..9f2cc845558 100644 --- a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts @@ -42,14 +42,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &usb_serial { status = "okay"; }; diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_appcpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_appcpu.dts index cd5cf5d0bf2..875d0eaea2a 100644 --- a/boards/m5stack/m5stack_core2/m5stack_core2_appcpu.dts +++ b/boards/m5stack/m5stack_core2/m5stack_core2_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts index 7cd5bc187c9..fec843884ca 100644 --- a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts +++ b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts @@ -73,14 +73,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &psram0 { reg = <0x3f800000 DT_SIZE_M(8)>; status = "disabled"; diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.dts b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.dts index a9e590b9bbf..ce947b57972 100644 --- a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.dts +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts index f832f4618ba..522518f7e07 100644 --- a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts @@ -45,14 +45,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &usb_serial { status = "okay"; }; diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.dts b/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.dts index 8b7e74fdd98..1911e4fe56d 100644 --- a/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.dts +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts index c1418ed51c3..b397c7d5b05 100644 --- a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts @@ -60,14 +60,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/m5stack/stamp_c3/stamp_c3.dts b/boards/m5stack/stamp_c3/stamp_c3.dts index 812c2aeaa86..e9d519a2a5f 100644 --- a/boards/m5stack/stamp_c3/stamp_c3.dts +++ b/boards/m5stack/stamp_c3/stamp_c3.dts @@ -38,10 +38,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu.dts b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu.dts index c52b029ea55..ae7a2e1e7f6 100644 --- a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu.dts +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts index 63070f08e1c..e092f9766b5 100644 --- a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts @@ -53,14 +53,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - uext_serial: &uart1 {}; uext_i2c: &i2c0 {}; uext_spi: &spi2 {}; diff --git a/boards/others/icev_wireless/icev_wireless.dts b/boards/others/icev_wireless/icev_wireless.dts index 8ed474200e0..60157808335 100644 --- a/boards/others/icev_wireless/icev_wireless.dts +++ b/boards/others/icev_wireless/icev_wireless.dts @@ -47,10 +47,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { current-speed = <115200>; pinctrl-0 = <&uart0_default>; diff --git a/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts b/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts index 8475709095b..943cda08b7d 100644 --- a/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts +++ b/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts @@ -29,10 +29,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu.dts b/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu.dts index 672c52a5cba..f2cf95742ac 100644 --- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu.dts +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu.dts @@ -17,14 +17,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &trng0 { status = "okay"; }; diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts index ae232f4d228..17c2ca3eeec 100644 --- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts @@ -38,14 +38,6 @@ }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &usb_serial { status = "okay"; }; diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu.dts b/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu.dts index 6bed6d38402..8501714220d 100644 --- a/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu.dts +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu.dts @@ -18,14 +18,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &ipm0 { status = "okay"; }; diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts b/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts index 2e748af71b9..62b657c44d0 100644 --- a/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts @@ -47,15 +47,6 @@ }; }; -&cpu0 { - clock-frequency = ; - cpu-power-states = <&light_sleep &deep_sleep>; -}; - -&cpu1 { - clock-frequency = ; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts index 50301f22c20..9b345338aa4 100644 --- a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts +++ b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts @@ -15,14 +15,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &flash0 { status = "okay"; reg = <0x0 DT_SIZE_M(16)>; diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts index 346c522142f..c00b23ba147 100644 --- a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts +++ b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts @@ -57,14 +57,6 @@ }; }; -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - &flash0 { status = "okay"; reg = <0x0 DT_SIZE_M(16)>; diff --git a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts index 53a598ad0de..14d6fd4b1d8 100644 --- a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts +++ b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts @@ -46,11 +46,6 @@ }; }; -&cpu0 { - clock-frequency = ; - cpu-power-states = <&deep_sleep &light_sleep>; -}; - &uart0 { status = "okay"; current-speed = <115200>; diff --git a/drivers/clock_control/clock_control_esp32.c b/drivers/clock_control/clock_control_esp32.c index 7aec123785d..594763846de 100644 --- a/drivers/clock_control/clock_control_esp32.c +++ b/drivers/clock_control/clock_control_esp32.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020 Mohamed ElShahawi. - * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2021-2024 Espressif Systems (Shanghai) Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,19 +10,21 @@ #define CPU_RESET_REASON RTC_SW_CPU_RESET #if defined(CONFIG_SOC_SERIES_ESP32) -#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx6 +#define DT_CPU_COMPAT espressif_xtensa_lx6 #undef CPU_RESET_REASON #define CPU_RESET_REASON SW_CPU_RESET #include #include #include +#include #elif defined(CONFIG_SOC_SERIES_ESP32S2) -#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7 +#define DT_CPU_COMPAT espressif_xtensa_lx7 #include #include #include +#include #elif defined(CONFIG_SOC_SERIES_ESP32S3) -#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7 +#define DT_CPU_COMPAT espressif_xtensa_lx7 #include #include #include @@ -30,67 +32,33 @@ #define DT_CPU_COMPAT espressif_riscv #include #include -#include -#include -#include #endif /* CONFIG_SOC_SERIES_ESP32xx */ +#include +#include + #include #include #include +#include #include -#include -#include -#include #include -#include -#include #include #include #include -#include +#include +#include +#include -struct esp32_clock_config { - int clk_src_sel; - uint32_t cpu_freq; - uint32_t xtal_freq_sel; - int xtal_div; -}; - -static int clock_control_esp32_on(const struct device *dev, - clock_control_subsys_t sys) -{ - ARG_UNUSED(dev); - periph_module_enable((periph_module_t)sys); - return 0; -} - -static int clock_control_esp32_off(const struct device *dev, - clock_control_subsys_t sys) -{ - ARG_UNUSED(dev); - periph_module_disable((periph_module_t)sys); - return 0; -} - -static int clock_control_esp32_async_on(const struct device *dev, - clock_control_subsys_t sys, - clock_control_cb_t cb, - void *user_data) -{ - ARG_UNUSED(dev); - ARG_UNUSED(sys); - ARG_UNUSED(cb); - ARG_UNUSED(user_data); - return -ENOTSUP; -} +#include +LOG_MODULE_REGISTER(clock_control, CONFIG_CLOCK_CONTROL_LOG_LEVEL); static enum clock_control_status clock_control_esp32_get_status(const struct device *dev, clock_control_subsys_t sys) { ARG_UNUSED(dev); uint32_t clk_en_reg = periph_ll_get_clk_en_reg((periph_module_t)sys); - uint32_t clk_en_mask = periph_ll_get_clk_en_mask((periph_module_t)sys); + uint32_t clk_en_mask = periph_ll_get_clk_en_mask((periph_module_t)sys); if (DPORT_GET_PERI_REG_MASK(clk_en_reg, clk_en_mask)) { return CLOCK_CONTROL_STATUS_ON; @@ -98,17 +66,45 @@ static enum clock_control_status clock_control_esp32_get_status(const struct dev return CLOCK_CONTROL_STATUS_OFF; } -static int clock_control_esp32_get_rate(const struct device *dev, - clock_control_subsys_t sub_system, +static int clock_control_esp32_on(const struct device *dev, clock_control_subsys_t sys) +{ + enum clock_control_status status = clock_control_esp32_get_status(dev, sys); + + if (status == CLOCK_CONTROL_STATUS_ON) { + return -EALREADY; + } + + periph_module_enable((periph_module_t)sys); + + return 0; +} + +static int clock_control_esp32_off(const struct device *dev, clock_control_subsys_t sys) +{ + enum clock_control_status status = clock_control_esp32_get_status(dev, sys); + + if (status == CLOCK_CONTROL_STATUS_ON) { + periph_module_disable((periph_module_t)sys); + } + + return 0; +} + +static int clock_control_esp32_get_rate(const struct device *dev, clock_control_subsys_t sys, uint32_t *rate) { - ARG_UNUSED(sub_system); + ARG_UNUSED(dev); - rtc_cpu_freq_config_t config; - - rtc_clk_cpu_freq_get_config(&config); - - *rate = config.freq_mhz; + switch ((int)sys) { + case ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST: + *rate = esp_clk_tree_lp_fast_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX); + break; + case ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW: + *rate = clk_hal_lp_slow_get_freq_hz(); + break; + default: + *rate = clk_hal_cpu_get_freq_hz(); + } return 0; } @@ -512,88 +508,218 @@ static void esp32_clock_perip_init(void) } #endif /* CONFIG_SOC_SERIES_ESP32C3 */ +static int esp32_select_rtc_slow_clk(uint8_t slow_clk) +{ + soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V; + uint32_t cal_val = 0; + /* number of times to repeat 32k XTAL calibration + * before giving up and switching to the internal RC + */ + int retry_32k_xtal = 3; + + do { + if (rtc_slow_clk_src == ESP32_RTC_SLOW_CLK_SRC_XTAL32K) { + /* 32k XTAL oscillator needs to be enabled and running before it can + * be used. Hardware doesn't have a direct way of checking if the + * oscillator is running. Here we use rtc_clk_cal function to count + * the number of main XTAL cycles in the given number of 32k XTAL + * oscillator cycles. If the 32k XTAL has not started up, calibration + * will time out, returning 0. + */ + LOG_DBG("waiting for 32k oscillator to start up"); + if (slow_clk == ESP32_RTC_SLOW_CLK_SRC_XTAL32K) { + rtc_clk_32k_enable(true); + } else if (slow_clk == ESP32_RTC_SLOW_CLK_32K_EXT_OSC) { + rtc_clk_32k_enable_external(); + } + /* When CONFIG_RTC_CLK_CAL_CYCLES is set to 0, clock calibration will not be + * performed at startup. + */ + if (CONFIG_RTC_CLK_CAL_CYCLES > 0) { + cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, CONFIG_RTC_CLK_CAL_CYCLES); + if (cal_val == 0) { + if (retry_32k_xtal-- > 0) { + continue; + } + LOG_ERR("32 kHz XTAL not found"); + return -ENODEV; + } + } + } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { + rtc_clk_8m_enable(true, true); + } + rtc_clk_slow_src_set(rtc_slow_clk_src); + + if (CONFIG_RTC_CLK_CAL_CYCLES > 0) { + cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, CONFIG_RTC_CLK_CAL_CYCLES); + } else { + const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; + + cal_val = (uint32_t)(cal_dividend / rtc_clk_slow_freq_get_hz()); + } + } while (cal_val == 0); + + LOG_DBG("RTC_SLOW_CLK calibration value: %d", cal_val); + + esp_clk_slowclk_cal_set(cal_val); + + return 0; +} + +static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cfg) +{ + rtc_cpu_freq_config_t old_config; + rtc_cpu_freq_config_t new_config; + rtc_clk_config_t rtc_clk_cfg = RTC_CLK_CONFIG_DEFAULT(); + uint32_t uart_clock_src_hz; + bool ret; + + rtc_clk_cfg.xtal_freq = cpu_cfg->xtal_freq; + rtc_clk_cfg.cpu_freq_mhz = cpu_cfg->cpu_freq; + + esp_rom_uart_tx_wait_idle(ESP_CONSOLE_UART_NUM); + + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap); + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, rtc_clk_cfg.clk_8m_dfreq); + +#if !defined(CONFIG_SOC_SERIES_ESP32) + /* Configure 150k clock division */ + rtc_clk_divider_set(rtc_clk_cfg.clk_rtc_clk_div); + + /* Configure 8M clock division */ + rtc_clk_8m_divider_set(rtc_clk_cfg.clk_8m_clk_div); +#else + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, rtc_clk_cfg.clk_8m_div - 1); +#endif + /* Reset (disable) i2c internal bus for all regi2c registers */ + regi2c_ctrl_ll_i2c_reset(); + /* Enable the internal bus used to configure BBPLL */ + regi2c_ctrl_ll_i2c_bbpll_enable(); +#if defined(CONFIG_SOC_SERIES_ESP32S2) || defined(CONFIG_SOC_SERIES_ESP32) + regi2c_ctrl_ll_i2c_apll_enable(); +#endif + +#if !defined(CONFIG_SOC_SERIES_ESP32S2) + rtc_clk_xtal_freq_update(rtc_clk_cfg.xtal_freq); +#endif + rtc_clk_apb_freq_update(rtc_clk_cfg.xtal_freq * MHZ(1)); + + /* Set CPU frequency */ + rtc_clk_cpu_freq_get_config(&old_config); + + ret = rtc_clk_cpu_freq_mhz_to_config(rtc_clk_cfg.cpu_freq_mhz, &new_config); + if (!ret || (new_config.source != cpu_cfg->clk_src)) { + LOG_ERR("invalid CPU frequency value"); + return -EINVAL; + } + + rtc_clk_cpu_freq_set_config(&new_config); + + /* Re-calculate the ccount to make time calculation correct. */ + esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * rtc_clk_cfg.cpu_freq_mhz / + old_config.freq_mhz); + + uart_clock_src_hz = esp_clk_apb_freq(); + +#if !defined(ESP_CONSOLE_UART_NONE) + esp_rom_uart_set_clock_baudrate(ESP_CONSOLE_UART_NUM, uart_clock_src_hz, + ESP_CONSOLE_UART_BAUDRATE); +#endif + return 0; +} + +static int clock_control_esp32_configure(const struct device *dev, clock_control_subsys_t sys, + void *data) +{ + + const struct esp32_clock_config *cfg = dev->config; + struct esp32_clock_config *new_cfg = data; + int ret = 0; + + switch ((int)sys) { + case ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST: + rtc_clk_fast_src_set(new_cfg->rtc.rtc_fast_clock_src); + break; + case ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW: + ret = esp32_select_rtc_slow_clk(new_cfg->rtc.rtc_slow_clock_src); + break; + case ESP32_CLOCK_CONTROL_SUBSYS_CPU: + /* Normalize frequency */ + new_cfg->cpu.xtal_freq = new_cfg->cpu.xtal_freq > MHZ(1) + ? new_cfg->cpu.xtal_freq / MHZ(1) + : new_cfg->cpu.xtal_freq; + new_cfg->cpu.cpu_freq = new_cfg->cpu.cpu_freq > MHZ(1) + ? new_cfg->cpu.cpu_freq / MHZ(1) + : new_cfg->cpu.cpu_freq; + ret = esp32_cpu_clock_configure(&new_cfg->cpu); + break; + default: + LOG_ERR("Unsupported subsystem %d", (int)sys); + return -EINVAL; + } + return ret; +} + static int clock_control_esp32_init(const struct device *dev) { const struct esp32_clock_config *cfg = dev->config; - rtc_cpu_freq_config_t old_config; - rtc_cpu_freq_config_t new_config; - bool res; + soc_reset_reason_t rst_reas; + rtc_config_t rtc_cfg = RTC_CONFIG_DEFAULT(); + bool ret; - /* wait uart output to be cleared */ - esp_rom_uart_tx_wait_idle(ESP_CONSOLE_UART_NUM); + rst_reas = esp_rom_get_reset_reason(0); +#if !defined(CONFIG_SOC_SERIES_ESP32) + if (rst_reas == RESET_REASON_CHIP_POWER_ON +#if SOC_EFUSE_HAS_EFUSE_RST_BUG + || rst_reas == RESET_REASON_CORE_EFUSE_CRC +#endif + ) { + rtc_cfg.cali_ocode = 1; + } +#endif + rtc_init(rtc_cfg); - /* reset default config to use dts config */ - if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) { - rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT(); - - clk_cfg.xtal_freq = cfg->xtal_freq_sel; - clk_cfg.cpu_freq_mhz = cfg->cpu_freq; - clk_cfg.slow_clk_src = rtc_clk_slow_freq_get(); - clk_cfg.fast_clk_src = rtc_clk_fast_freq_get(); - rtc_clk_init(clk_cfg); + ret = esp32_cpu_clock_configure(&cfg->cpu); + if (ret) { + LOG_ERR("Failed to configure CPU clock"); + return ret; } - rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M); + rtc_clk_fast_src_set(cfg->rtc.rtc_fast_clock_src); - rtc_clk_cpu_freq_get_config(&old_config); - - const uint32_t old_freq_mhz = old_config.freq_mhz; - const uint32_t new_freq_mhz = cfg->cpu_freq; - - res = rtc_clk_cpu_freq_mhz_to_config(cfg->cpu_freq, &new_config); - if (!res) { - return -ENOTSUP; + ret = esp32_select_rtc_slow_clk(cfg->rtc.rtc_slow_clock_src); + if (ret) { + LOG_ERR("Failed to configure RTC clock"); + return ret; } - if (cfg->xtal_div >= 0) { - new_config.div = cfg->xtal_div; - } - - if (cfg->clk_src_sel >= 0) { - new_config.source = cfg->clk_src_sel; - } - - /* set new configuration */ - rtc_clk_cpu_freq_set_config(&new_config); - - /* Re-calculate the ccount to make time calculation correct */ - esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz); - esp32_clock_perip_init(); - uint32_t clock_hz = esp_clk_apb_freq(); -#if ESP_ROM_UART_CLK_IS_XTAL - clock_hz = esp_clk_xtal_freq(); -#endif - -#if !defined(ESP_CONSOLE_UART_NONE) - esp_rom_uart_set_clock_baudrate(ESP_CONSOLE_UART_NUM, - clock_hz, ESP_CONSOLE_UART_BAUDRATE); -#endif return 0; } static const struct clock_control_driver_api clock_control_esp32_api = { .on = clock_control_esp32_on, .off = clock_control_esp32_off, - .async_on = clock_control_esp32_async_on, .get_rate = clock_control_esp32_get_rate, .get_status = clock_control_esp32_get_status, + .configure = clock_control_esp32_configure, }; -#define ESP32_CLOCK_SOURCE \ - COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source), \ - (DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source)), (-1)) +static const struct esp32_cpu_clock_config esp32_cpu_clock_config0 = { + .clk_src = DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source), + .cpu_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency) / MHZ(1)), + .xtal_freq = ((DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq)) / MHZ(1)), +}; -#define ESP32_CLOCK_XTAL_DIV \ - COND_CODE_1(DT_NODE_HAS_PROP(0, xtal_div), \ - (DT_INST_PROP(0, xtal_div)), (-1)) +static const struct esp32_rtc_clock_config esp32_rtc_clock_config0 = { + .rtc_fast_clock_src = DT_PROP(DT_INST(0, espressif_esp32_rtc), fast_clk_src), + .rtc_slow_clock_src = DT_PROP(DT_INST(0, espressif_esp32_rtc), slow_clk_src) +}; static const struct esp32_clock_config esp32_clock_config0 = { - .clk_src_sel = ESP32_CLOCK_SOURCE, - .cpu_freq = DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency) / 1000000, - .xtal_freq_sel = DT_INST_PROP(0, xtal_freq), - .xtal_div = ESP32_CLOCK_XTAL_DIV + .cpu = esp32_cpu_clock_config0, + .rtc = esp32_rtc_clock_config0 }; DEVICE_DT_DEFINE(DT_NODELABEL(rtc), diff --git a/drivers/counter/Kconfig.esp32_tmr b/drivers/counter/Kconfig.esp32_tmr index 52f1c55c695..93f6e2503e2 100644 --- a/drivers/counter/Kconfig.esp32_tmr +++ b/drivers/counter/Kconfig.esp32_tmr @@ -10,3 +10,11 @@ config COUNTER_TMR_ESP32 help Enables the Counter driver API based on Espressif's General Purpose Timers for ESP32 series devices. + +config COUNTER_TMR_RTC_ESP32 + bool "ESP32 Counter Driver based on GP-Timers" + default y + depends on DT_HAS_ESPRESSIF_ESP32_RTC_TIMER_ENABLED + help + Enables the Counter driver API based on Espressif's General + Purpose Timers for ESP32 series devices. diff --git a/drivers/counter/counter_esp32_rtc.c b/drivers/counter/counter_esp32_rtc.c index 0b7e8bbbb27..379a9f0e57b 100644 --- a/drivers/counter/counter_esp32_rtc.c +++ b/drivers/counter/counter_esp32_rtc.c @@ -12,11 +12,15 @@ */ #include "soc/rtc_cntl_reg.h" #include "soc/rtc.h" +#include +#include #include #include #include #include +#include +#include #if defined(CONFIG_SOC_SERIES_ESP32C3) #include @@ -38,21 +42,25 @@ static void counter_esp32_isr(void *arg); struct counter_esp32_config { struct counter_config_info counter_info; int irq_source; + const struct device *clock_dev; }; struct counter_esp32_data { struct counter_alarm_cfg alarm_cfg; uint32_t ticks; + uint32_t clk_src_freq; }; static int counter_esp32_init(const struct device *dev) { const struct counter_esp32_config *cfg = dev->config; + struct counter_esp32_data *data = dev->data; - /* SLOW_CK is the default clk source */ - if (cfg->counter_info.freq != rtc_clk_slow_freq_get_hz()) { - return -EINVAL; - } + + /* RTC_SLOW_CLK is the default clk source */ + clock_control_get_rate(cfg->clock_dev, + (clock_control_subsys_t)ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW, + &data->clk_src_freq); esp_intr_alloc(cfg->irq_source, 0, @@ -80,22 +88,14 @@ static int counter_esp32_stop(const struct device *dev) * reset, will not stop or reset the RTC timer * ESP32 TRM v4.6 sec. 31.3.11 */ - return -ENOTSUP; + return 0; } static int counter_esp32_get_value(const struct device *dev, uint32_t *ticks) { ARG_UNUSED(dev); - SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); -#if defined(CONFIG_SOC_SERIES_ESP32) - while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) { - /* might take 1 RTC slowclk period, don't flood RTC bus */ - k_sleep(K_USEC(1)); - } - SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR); -#endif - *ticks = (uint32_t) READ_PERI_REG(RTC_CNTL_TIME0_REG); + *ticks = (uint32_t) rtc_cntl_ll_get_rtc_time(); return 0; } @@ -106,26 +106,32 @@ static int counter_esp32_set_alarm(const struct device *dev, uint8_t chan_id, ARG_UNUSED(chan_id); struct counter_esp32_data *data = dev->data; uint32_t now; + uint32_t ticks = 0; + +#if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32C3) + /* In ESP32/C3 Series the min possible value is 30 us*/ + if (counter_ticks_to_us(dev, alarm_cfg->ticks) < 30) { + return -EINVAL; + } +#endif + data->alarm_cfg.callback = alarm_cfg->callback; + data->alarm_cfg.user_data = alarm_cfg->user_data; counter_esp32_get_value(dev, &now); - if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) { - WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, (now + alarm_cfg->ticks)); - } else { - WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, alarm_cfg->ticks); - } + ticks = (alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) ? alarm_cfg->ticks + : now + alarm_cfg->ticks; + + rtc_cntl_ll_set_wakeup_timer(ticks); /* RTC main timer set alarm value */ CLEAR_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, 0xffffffff); - /* RTC main timer interrupt enable */ - SET_PERI_REG_MASK(RTC_CNTL_INT_ENA_REG, RTC_CNTL_MAIN_TIMER_INT_ENA); - /* RTC main timer set alarm enable */ SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN); - data->alarm_cfg.callback = alarm_cfg->callback; - data->alarm_cfg.user_data = alarm_cfg->user_data; + /* RTC main timer interrupt enable */ + SET_PERI_REG_MASK(RTC_CNTL_INT_ENA_REG, RTC_CNTL_MAIN_TIMER_INT_ENA); return 0; } @@ -172,9 +178,16 @@ static uint32_t counter_esp32_get_pending_int(const struct device *dev) */ static uint32_t counter_esp32_get_top_value(const struct device *dev) { - const struct counter_config_info *info = dev->config; + const struct counter_esp32_config *cfg = dev->config; - return info->max_top_value; + return cfg->counter_info.max_top_value; +} + +static uint32_t counter_esp32_get_freq(const struct device *dev) +{ + struct counter_esp32_data *data = dev->data; + + return data->clk_src_freq; } static struct counter_esp32_data counter_data; @@ -182,10 +195,10 @@ static struct counter_esp32_data counter_data; static const struct counter_esp32_config counter_config = { .counter_info = { .max_top_value = UINT32_MAX, - .freq = DT_INST_PROP(0, slow_clk_freq), .flags = COUNTER_CONFIG_INFO_COUNT_UP, .channels = 1 }, + .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)), .irq_source = DT_INST_IRQN(0), }; @@ -198,6 +211,7 @@ static const struct counter_driver_api rtc_timer_esp32_api = { .set_top_value = counter_esp32_set_top_value, .get_pending_int = counter_esp32_get_pending_int, .get_top_value = counter_esp32_get_top_value, + .get_freq = counter_esp32_get_freq, }; static void counter_esp32_isr(void *arg) @@ -222,6 +236,6 @@ DEVICE_DT_INST_DEFINE(0, NULL, &counter_data, &counter_config, - PRE_KERNEL_1, + POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY, &rtc_timer_esp32_api); diff --git a/drivers/timer/esp32_sys_timer.c b/drivers/timer/esp32_sys_timer.c index 04080729911..0fa888f6745 100644 --- a/drivers/timer/esp32_sys_timer.c +++ b/drivers/timer/esp32_sys_timer.c @@ -156,5 +156,5 @@ static int sys_clock_driver_init(void) return 0; } -SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, +SYS_INIT(sys_clock_driver_init, PRE_KERNEL_1, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY); diff --git a/dts/bindings/clock/espressif,esp32-rtc.yaml b/dts/bindings/clock/espressif,esp32-rtc.yaml index e30b027a466..c5ba5023983 100644 --- a/dts/bindings/clock/espressif,esp32-rtc.yaml +++ b/dts/bindings/clock/espressif,esp32-rtc.yaml @@ -11,14 +11,32 @@ properties: reg: required: true - xtal-freq: + fast-clk-src: type: int required: true - description: Value of the external XTAL connected to ESP32. + description: | + RTC fast clock source. + - 0: ESP32_RTC_FAST_CLK_SRC_XTAL_D2 - Main XTAL divided by 2 (C3/S3) + ESP32_RTC_FAST_CLK_SRC_XTAL_D4 Main XTAL divided by 4 (ESP32/S2) + - 1: ESP32_RTC_FAST_CLK_SRC_RC_FAST - 8 MHz + enum: + - 0 + - 1 - xtal-div: + slow-clk-src: type: int - description: Divisor value for XTAL Clock, CPU_CLK = XTAL_FREQ / xtal-div + required: true + description: | + RTC slow clock source. Default to + - 0: ESP32_RTC_SLOW_CLK_SRC_RC_SLOW - 136 KHz (C3/S3) - 90 kHz (S2) - 150 kHz (ESP32) + - 1: ESP32_RTC_SLOW_CLK_SRC_XTAL32K - 32,768U KHz + - 2: ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 - 17,5 MHz + - 9: ESP32_RTC_SLOW_CLK_32K_EXT_OSC - External 32k oscillator connected to 32K_XP pin + enum: + - 0 + - 1 + - 2 + - 9 "#clock-cells": const: 1 diff --git a/dts/bindings/counter/espressif,esp32-rtc-timer.yaml b/dts/bindings/counter/espressif,esp32-rtc-timer.yaml index 86d5cd68876..a8bc1c1165f 100644 --- a/dts/bindings/counter/espressif,esp32-rtc-timer.yaml +++ b/dts/bindings/counter/espressif,esp32-rtc-timer.yaml @@ -15,11 +15,4 @@ description: | include: base.yaml -properties: - slow-clk-freq: - description: | - The slow clock input frequency for the RTC Timer. - type: int - required: true - compatible: "espressif,esp32-rtc-timer" diff --git a/dts/bindings/cpu/espressif,riscv.yaml b/dts/bindings/cpu/espressif,riscv.yaml index a93894cd946..374d51c6a2f 100644 --- a/dts/bindings/cpu/espressif,riscv.yaml +++ b/dts/bindings/cpu/espressif,riscv.yaml @@ -9,5 +9,24 @@ include: riscv,cpus.yaml properties: clock-source: + required: true type: int - description: cpu clock source + description: | + Defines the CPU clock source, each corresponding to different frequencies: + - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz. + - 1: ESP32_CPU_CLK_SRC_PLL - Utilizes an internal PLL which operates at either + 320 MHz or 480 MHz. + - 2: ESP32_CPU_CLK_SRC_RC_FAST - Employs an internal fast RC oscillator with + frequency of 17.5 MHz. + enum: + - 0 + - 1 + - 2 + + xtal-freq: + required: true + type: int + description: Value of the external XTAL connected to ESP32. This is typically 40 MHz. + enum: + - 40000000 + - 32000000 diff --git a/dts/bindings/cpu/espressif,xtensa-lx6.yaml b/dts/bindings/cpu/espressif,xtensa-lx6.yaml new file mode 100644 index 00000000000..24dd830cb01 --- /dev/null +++ b/dts/bindings/cpu/espressif,xtensa-lx6.yaml @@ -0,0 +1,34 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: Espressif Xtensa CPU + +compatible: "espressif,xtensa-lx6" + +include: cdns,tensilica-xtensa-lx6.yaml + +properties: + clock-source: + required: true + type: int + description: | + Defines the CPU clock source, each corresponding to different frequencies: + - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz. + - 1: ESP32_CPU_CLK_SRC_PLL - Utilizes an internal PLL which operates at either + 320 MHz or 480 MHz. + - 2: ESP32_CPU_CLK_SRC_RC_FAST - Employs an internal fast RC oscillator with + frequency of 17.5 MHz. 8 MHz for ESP32S2. + - 3: APLL_CLK - 16 Mhz ~ 128 MHz + enum: + - 0 + - 1 + - 2 + - 3 + + xtal-freq: + type: int + required: true + description: Value of the external XTAL connected to ESP32. + enum: + - 40000000 + - 32000000 diff --git a/dts/bindings/cpu/espressif,xtensa-lx7.yaml b/dts/bindings/cpu/espressif,xtensa-lx7.yaml new file mode 100644 index 00000000000..33c6503122b --- /dev/null +++ b/dts/bindings/cpu/espressif,xtensa-lx7.yaml @@ -0,0 +1,34 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: Espressif Xtensa CPU + +compatible: "espressif,xtensa-lx7" + +include: cdns,tensilica-xtensa-lx7.yaml + +properties: + clock-source: + type: int + required: true + description: | + Defines the CPU clock source, each corresponding to different frequencies: + - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz. + - 1: ESP32_CPU_CLK_SRC_PLL - Utilizes an internal PLL which operates at either + 320 MHz or 480 MHz. + - 2: ESP32_CPU_CLK_SRC_RC_FAST - Employs an internal fast RC oscillator with + frequency of 17.5 MHz. 8 MHz for ESP32S2. + - 3: APLL_CLK - 16 Mhz ~ 128 MHz (ESP32S2 Only) + enum: + - 0 + - 1 + - 2 + - 3 + + xtal-freq: + type: int + required: true + description: Value of the external XTAL connected to ESP32. + enum: + - 40000000 + - 32000000 diff --git a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi index 6ad2f612866..7c0962bec7a 100644 --- a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi +++ b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include +#include #include #include #include @@ -35,6 +36,9 @@ riscv,isa = "rv32imc_zicsr"; reg = <0>; cpu-power-states = <&light_sleep &deep_sleep>; + clock-source = ; + clock-frequency = ; + xtal-freq = ; }; power-states { @@ -95,17 +99,19 @@ rtc: rtc@60008000 { compatible = "espressif,esp32-rtc"; reg = <0x60008000 0x1000>; - xtal-freq = ; + fast-clk-src = ; + slow-clk-src = ; #clock-cells = <1>; status = "okay"; + }; - rtc_timer: rtc_timer { - compatible = "espressif,esp32-rtc-timer"; - slow-clk-freq = ; - interrupts = ; - interrupt-parent = <&intc>; - status = "okay"; - }; + rtc_timer: rtc_timer@60008004 { + reg = <0x60008004 0xC>; + compatible = "espressif,esp32-rtc-timer"; + clocks = <&rtc ESP32_MODULE_MAX>; + interrupts = ; + interrupt-parent = <&intc>; + status = "okay"; }; flash: flash-controller@60002000 { diff --git a/dts/xtensa/espressif/esp32/esp32_common.dtsi b/dts/xtensa/espressif/esp32/esp32_common.dtsi index 82a92ed00a8..d721dd08a2c 100644 --- a/dts/xtensa/espressif/esp32/esp32_common.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_common.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include +#include #include #include #include @@ -26,15 +27,21 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "cdns,tensilica-xtensa-lx6"; + compatible = "espressif,xtensa-lx6"; reg = <0>; cpu-power-states = <&light_sleep &deep_sleep>; + clock-source = ; + clock-frequency = ; + xtal-freq = ; }; cpu1: cpu@1 { device_type = "cpu"; - compatible = "cdns,tensilica-xtensa-lx6"; + compatible = "espressif,xtensa-lx6"; reg = <1>; + clock-source = ; + clock-frequency = ; + xtal-freq = ; }; power-states { @@ -107,17 +114,20 @@ rtc: rtc@3ff48000 { compatible = "espressif,esp32-rtc"; reg = <0x3ff48000 0x0D8>; - xtal-freq = ; + fast-clk-src = ; + slow-clk-src = ; #clock-cells = <1>; status = "okay"; - rtc_timer: rtc_timer { - compatible = "espressif,esp32-rtc-timer"; - slow-clk-freq = ; - interrupts = ; - interrupt-parent = <&intc>; - status = "okay"; - }; + }; + + rtc_timer: rtc_timer@3ff48004 { + reg = <0x3ff48004 0xC>; + compatible = "espressif,esp32-rtc-timer"; + clocks = <&rtc ESP32_MODULE_MAX>; + interrupts = ; + interrupt-parent = <&intc>; + status = "okay"; }; flash: flash-controller@3ff42000 { diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi index 1bb8c000ed5..e8491c338e7 100644 --- a/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi +++ b/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include +#include #include #include #include @@ -32,9 +33,12 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "cdns,tensilica-xtensa-lx7"; + compatible = "espressif,xtensa-lx7"; reg = <0>; cpu-power-states = <&light_sleep &deep_sleep>; + clock-source = ; + clock-frequency = ; + xtal-freq = ; }; power-states { @@ -86,17 +90,20 @@ rtc: rtc@3f408000 { compatible = "espressif,esp32-rtc"; reg = <0x3f408000 0x0D8>; - xtal-freq = ; + fast-clk-src = ; + slow-clk-src = ; #clock-cells = <1>; status = "okay"; - rtc_timer: rtc_timer { - compatible = "espressif,esp32-rtc-timer"; - slow-clk-freq = ; - interrupts = ; - interrupt-parent = <&intc>; - status = "okay"; - }; + }; + + rtc_timer: rtc_timer@3f408004 { + reg = <0x3f408004 0xC>; + compatible = "espressif,esp32-rtc-timer"; + clocks = <&rtc ESP32_MODULE_MAX>; + interrupts = ; + interrupt-parent = <&intc>; + status = "okay"; }; flash: flash-controller@3f402000 { diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi index b02d38410ad..62135a34ac3 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ #include +#include #include #include #include @@ -30,15 +31,21 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "cdns,tensilica-xtensa-lx7"; + compatible = "espressif,xtensa-lx7"; reg = <0>; cpu-power-states = <&light_sleep &deep_sleep>; + clock-source = ; + clock-frequency = ; + xtal-freq = ; }; cpu1: cpu@1 { device_type = "cpu"; - compatible = "cdns,tensilica-xtensa-lx7"; + compatible = "espressif,xtensa-lx7"; reg = <1>; + clock-source = ; + clock-frequency = ; + xtal-freq = ; }; power-states { @@ -100,17 +107,20 @@ rtc: rtc@60021000 { compatible = "espressif,esp32-rtc"; reg = <0x60021000 0x2000>; - xtal-freq = ; + fast-clk-src = ; + slow-clk-src = ; #clock-cells = <1>; status = "okay"; - rtc_timer: rtc_timer { - compatible = "espressif,esp32-rtc-timer"; - slow-clk-freq = ; - interrupts = ; - interrupt-parent = <&intc>; - status = "okay"; - }; + }; + + rtc_timer: rtc_timer@60008004 { + reg = <0x60008004 0xC>; + compatible = "espressif,esp32-rtc-timer"; + clocks = <&rtc ESP32_MODULE_MAX>; + interrupts = ; + interrupt-parent = <&intc>; + status = "okay"; }; flash: flash-controller@60002000 { diff --git a/include/zephyr/drivers/clock_control/esp32_clock_control.h b/include/zephyr/drivers/clock_control/esp32_clock_control.h new file mode 100644 index 00000000000..d74b2c0aeff --- /dev/null +++ b/include/zephyr/drivers/clock_control/esp32_clock_control.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_ESP32_CLOCK_CONTROL_H_ +#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_ESP32_CLOCK_CONTROL_H_ + +#if defined(CONFIG_SOC_SERIES_ESP32) +#include +#elif defined(CONFIG_SOC_SERIES_ESP32S2) +#include +#elif defined(CONFIG_SOC_SERIES_ESP32S3) +#include +#elif defined(CONFIG_SOC_SERIES_ESP32C3) +#include +#endif /* CONFIG_SOC_SERIES_ESP32xx */ + +#define ESP32_CLOCK_CONTROL_SUBSYS_CPU 50 +#define ESP32_CLOCK_CONTROL_SUBSYS_RTC_FAST 51 +#define ESP32_CLOCK_CONTROL_SUBSYS_RTC_SLOW 52 + +struct esp32_cpu_clock_config { + int clk_src; + uint32_t cpu_freq; + uint32_t xtal_freq; +}; + +struct esp32_rtc_clock_config { + uint32_t rtc_fast_clock_src; + uint32_t rtc_slow_clock_src; +}; + +struct esp32_clock_config { + struct esp32_cpu_clock_config cpu; + struct esp32_rtc_clock_config rtc; +}; + +#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_ESP32_CLOCK_CONTROL_H_ */ diff --git a/include/zephyr/dt-bindings/clock/esp32_clock.h b/include/zephyr/dt-bindings/clock/esp32_clock.h index 99ab3c7004b..db4abbf02f7 100644 --- a/include/zephyr/dt-bindings/clock/esp32_clock.h +++ b/include/zephyr/dt-bindings/clock/esp32_clock.h @@ -8,32 +8,37 @@ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_ -/* System Clock Source */ -#define ESP32_CLK_SRC_XTAL 0U -#define ESP32_CLK_SRC_PLL 1U -#define ESP32_CLK_SRC_RTC8M 2U -#define ESP32_CLK_SRC_APLL 3U +/* Supported CPU clock Sources */ +#define ESP32_CPU_CLK_SRC_XTAL 0U +#define ESP32_CPU_CLK_SRC_PLL 1U +#define ESP32_CLK_SRC_RC_FAST 2U +#define ESP32_CLK_SRC_APLL_CLK 3U -/* Supported CPU Frequencies */ -#define ESP32_CLK_CPU_26M 26000000 -#define ESP32_CLK_CPU_40M 40000000 -#define ESP32_CLK_CPU_80M 80000000 -#define ESP32_CLK_CPU_160M 160000000 -#define ESP32_CLK_CPU_240M 240000000 +/* Supported PLL CPU frequencies */ +#define ESP32_CLK_CPU_PLL_80M 80000000 +#define ESP32_CLK_CPU_PLL_160M 160000000 +#define ESP32_CLK_CPU_PLL_240M 240000000 +#define ESP32_CLK_CPU_RC_FAST_FREQ 1062500 -/* Supported XTAL Frequencies */ -#define ESP32_CLK_XTAL_24M 24 -#define ESP32_CLK_XTAL_26M 26 -#define ESP32_CLK_XTAL_40M 40 -#define ESP32_CLK_XTAL_AUTO 0 +/* Supported XTAL frequencies */ +#define ESP32_CLK_XTAL_24M 24000000 +#define ESP32_CLK_XTAL_26M 26000000 +#define ESP32_CLK_XTAL_40M 40000000 -/* Supported RTC fast clock frequencies */ -#define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U +/* Supported RTC fast clock sources */ +#define ESP32_RTC_FAST_CLK_SRC_XTAL_D4 0 +#define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1 -/* Supported RTC slow clock frequencies */ -#define ESP32_RTC_SLOW_CLK_FREQ_150K 150000U -#define ESP32_RTC_SLOW_CLK_FREQ_32K 32000U -#define ESP32_RTC_SLOW_CLK_FREQ_8MD256 (ESP32_RTC_FAST_CLK_FREQ_8M / 256) +/* Supported RTC slow clock sources */ +#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 +#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1 +#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2 +#define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9 + +/* RTC slow clock frequencies */ +#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 150000 +#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768 +#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 33203 /* Modules IDs * These IDs are actually offsets in CLK and RST Control registers. diff --git a/include/zephyr/dt-bindings/clock/esp32c3_clock.h b/include/zephyr/dt-bindings/clock/esp32c3_clock.h index 6b5b3de1227..d0a266e424f 100644 --- a/include/zephyr/dt-bindings/clock/esp32c3_clock.h +++ b/include/zephyr/dt-bindings/clock/esp32c3_clock.h @@ -7,28 +7,34 @@ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C3_H_ -/* System Clock Source */ -#define ESP32_CLK_SRC_XTAL 0U -#define ESP32_CLK_SRC_PLL 1U -#define ESP32_CLK_SRC_RTC8M 2U -#define ESP32_CLK_SRC_APLL 3U +/* Supported CPU clock Sources */ +#define ESP32_CPU_CLK_SRC_XTAL 0U +#define ESP32_CPU_CLK_SRC_PLL 1U +#define ESP32_CLK_SRC_RC_FAST 2U -/* Supported CPU Frequencies */ -#define ESP32_CLK_CPU_80M 80000000 -#define ESP32_CLK_CPU_160M 160000000 +/* Supported CPU frequencies */ +#define ESP32_CLK_CPU_PLL_80M 80000000 +#define ESP32_CLK_CPU_PLL_160M 160000000 +#define ESP32_CLK_CPU_RC_FAST_FREQ 17500000 -/* Supported XTAL Frequencies */ -#define ESP32_CLK_XTAL_32M 32 -#define ESP32_CLK_XTAL_40M 40 +/* Supported XTAL frequencies */ +#define ESP32_CLK_XTAL_32M 32000000 +#define ESP32_CLK_XTAL_40M 40000000 -/* Supported RTC fast clock frequencies */ -#define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U -#define ESP32_RTC_FAST_CLK_FREQ_APPROX ESP32_RTC_FAST_CLK_FREQ_8M +/* Supported RTC fast clock sources */ +#define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 0 +#define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1 -/* Supported RTC slow clock frequencies */ -#define ESP32_RTC_SLOW_CLK_FREQ_90K 90000U -#define ESP32_RTC_SLOW_CLK_FREQ_8MD256 (ESP32_RTC_FAST_CLK_FREQ_APPROX / 256) -#define ESP32_RTC_SLOW_CLK_FREQ_32K 32768U +/* Supported RTC slow clock sources */ +#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 +#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1 +#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2 +#define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9 + +/* RTC slow clock frequencies */ +#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000 +#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768 +#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 68359 /* Modules IDs * These IDs are actually offsets in CLK and RST Control registers. diff --git a/include/zephyr/dt-bindings/clock/esp32s2_clock.h b/include/zephyr/dt-bindings/clock/esp32s2_clock.h index aa9eb90de62..5fc57c65d70 100644 --- a/include/zephyr/dt-bindings/clock/esp32s2_clock.h +++ b/include/zephyr/dt-bindings/clock/esp32s2_clock.h @@ -7,30 +7,35 @@ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S2_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S2_H_ -/* System Clock Source */ -#define ESP32_CLK_SRC_XTAL 0U -#define ESP32_CLK_SRC_PLL 1U -#define ESP32_CLK_SRC_RTC8M 2U -#define ESP32_CLK_SRC_APLL 3U +/* Supported CPU clock Sources */ +#define ESP32_CPU_CLK_SRC_XTAL 0U +#define ESP32_CPU_CLK_SRC_PLL 1U +#define ESP32_CLK_SRC_RC_FAST 2U +#define ESP32_CLK_SRC_APLL_CLK 3U -/* Supported CPU Frequencies */ -#define ESP32_CLK_CPU_26M 26000000 -#define ESP32_CLK_CPU_40M 40000000 -#define ESP32_CLK_CPU_80M 80000000 -#define ESP32_CLK_CPU_160M 160000000 -#define ESP32_CLK_CPU_240M 240000000 +/* Supported PLL CPU frequencies */ +#define ESP32_CLK_CPU_PLL_80M 80000000 +#define ESP32_CLK_CPU_PLL_160M 160000000 +#define ESP32_CLK_CPU_PLL_240M 240000000 +#define ESP32_CLK_CPU_RC_FAST_FREQ 8500000 -/* Supported XTAL Frequencies */ -#define ESP32_CLK_XTAL_40M 40 +/* Supported XTAL frequencies */ +#define ESP32_CLK_XTAL_40M 40000000 -/* Supported RTC fast clock frequencies */ -#define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U -#define ESP32_RTC_FAST_CLK_FREQ_APPROX ESP32_RTC_FAST_CLK_FREQ_8M +/* Supported RTC fast clock sources */ +#define ESP32_RTC_FAST_CLK_SRC_XTAL_D4 0 +#define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1 -/* Supported RTC slow clock frequencies */ -#define ESP32_RTC_SLOW_CLK_FREQ_90K 90000U -#define ESP32_RTC_SLOW_CLK_FREQ_8MD256 (ESP32_RTC_FAST_CLK_FREQ_APPROX / 256) -#define ESP32_RTC_SLOW_CLK_FREQ_32K 32768U +/* Supported RTC slow clock sources */ +#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 +#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1 +#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2 +#define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9 + +/* RTC slow clock frequencies */ +#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 90000 +#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768 +#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 33203 /* Modules IDs * These IDs are actually offsets in CLK and RST Control registers. diff --git a/include/zephyr/dt-bindings/clock/esp32s3_clock.h b/include/zephyr/dt-bindings/clock/esp32s3_clock.h index 68980d0c8bf..9c4bb8364ec 100644 --- a/include/zephyr/dt-bindings/clock/esp32s3_clock.h +++ b/include/zephyr/dt-bindings/clock/esp32s3_clock.h @@ -7,30 +7,35 @@ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S3_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S3_H_ -/* System Clock Source */ -#define ESP32_CLK_SRC_XTAL 0U -#define ESP32_CLK_SRC_PLL 1U -#define ESP32_CLK_SRC_RTC8M 2U -#define ESP32_CLK_SRC_APLL 3U +/* Supported CPU clock Sources */ +#define ESP32_CPU_CLK_SRC_XTAL 0U +#define ESP32_CPU_CLK_SRC_PLL 1U +#define ESP32_CLK_SRC_RC_FAST 2U -/* Supported CPU Frequencies */ -#define ESP32_CLK_CPU_26M 26000000 -#define ESP32_CLK_CPU_40M 40000000 -#define ESP32_CLK_CPU_80M 80000000 -#define ESP32_CLK_CPU_160M 160000000 -#define ESP32_CLK_CPU_240M 240000000 +/* Supported PLL CPU frequencies */ +#define ESP32_CLK_CPU_PLL_80M 80000000 +#define ESP32_CLK_CPU_PLL_160M 160000000 +#define ESP32_CLK_CPU_PLL_240M 240000000 +#define ESP32_CLK_CPU_RC_FAST_FREQ 17500000 -/* Supported XTAL Frequencies */ -#define ESP32_CLK_XTAL_32M 32 -#define ESP32_CLK_XTAL_40M 40 +/* Supported XTAL frequencies */ +#define ESP32_CLK_XTAL_32M 32000000 +#define ESP32_CLK_XTAL_40M 40000000 -/* Supported RTC fast clock frequencies */ -#define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U +/* Supported RTC fast clock sources */ +#define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 0 +#define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1 -/* Supported RTC slow clock frequencies */ -#define ESP32_RTC_SLOW_CLK_FREQ_150K 150000U -#define ESP32_RTC_SLOW_CLK_FREQ_32K 32000U -#define ESP32_RTC_SLOW_CLK_FREQ_8MD256 (ESP32_RTC_FAST_CLK_FREQ_8M / 256) +/* Supported RTC slow clock sources */ +#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 +#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1 +#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2 +#define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9 + +/* RTC slow clock frequencies */ +#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000 +#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768 +#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 68359 /* Modules IDs * These IDs are actually offsets in CLK and RST Control registers. diff --git a/soc/espressif/Kconfig b/soc/espressif/Kconfig index 1917c3b432b..1efa0169ee6 100644 --- a/soc/espressif/Kconfig +++ b/soc/espressif/Kconfig @@ -35,13 +35,25 @@ endmenu menu "RTC Clock Config" -config ESP_SYSTEM_RTC_EXT_XTAL - bool +config RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 + range 0 32766 + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. -config ESP_SYSTEM_RTC_EXT_OSC - bool + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: -rsource "*/Kconfig.rtc" + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. endmenu endif # SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/soc/espressif/esp32/Kconfig.rtc b/soc/espressif/esp32/Kconfig.rtc deleted file mode 100644 index ea14eeaf098..00000000000 --- a/soc/espressif/esp32/Kconfig.rtc +++ /dev/null @@ -1,94 +0,0 @@ -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32 - -choice RTC_CLK_SRC - prompt "RTC clock source" - default RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - - "Internal 150kHz oscillator" option provides lowest deep sleep current - consumption, and does not require extra external components. However - frequency stability with respect to temperature is poor, so time may - drift in deep/light sleep modes. - - "External 32kHz crystal" provides better frequency stability, at the - expense of slightly higher (1uA) deep sleep current consumption. - - "External 32kHz oscillator" allows using 32kHz clock generated by an - external circuit. In this case, external clock signal must be connected - to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, - and <1V in case of square wave signal. Common mode voltage should be - 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. - Additionally, 1nF capacitor must be connected between 32K_XP pin and - ground. 32K_XP pin can not be used as a GPIO in this case. - - "Internal 8.5MHz oscillator divided by 256" option results in higher - deep sleep current (by 5uA) but has better frequency stability than - the internal 150kHz oscillator. It does not require external components. - -config RTC_CLK_SRC_INT_RC - bool "Internal 150kHz RC oscillator" - -config RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XN pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config RTC_CLK_SRC_INT_8MD256 - bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)" - -endchoice # RTC_CLK_SRC - -config RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 - default 1024 if RTC_CLK_SRC_INT_RC - range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 - range 0 32766 if RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -config RTC_XTAL_CAL_RETRY - int "Number of attempts to repeat 32k XTAL calibration" - default 1 - depends on RTC_CLK_SRC_EXT_CRYS - help - Number of attempts to repeat 32k XTAL calibration - before giving up and switching to the internal RC. - Increase this option if the 32k crystal oscillator - does not start and switches to internal RC. - -config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES - int "Bootstrap cycles for external 32kHz crystal" - depends on ESP_SYSTEM_RTC_EXT_XTAL - default 5 - range 0 32768 - help - To reduce the startup time of an external RTC crystal, - we bootstrap it with a 32kHz square wave for a fixed number of cycles. - Setting 0 will disable bootstrapping (if disabled, the crystal may take - longer to start up or fail to oscillate under some conditions). - - If this value is too high, a faulty crystal may initially start and then fail. - If this value is too low, an otherwise good crystal may not start. - - To accurately determine if the crystal has started, - set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000). - -endif # SOC_SERIES_ESP32 diff --git a/soc/espressif/esp32/soc.c b/soc/espressif/esp32/soc.c index 1c6e0eaa7db..bec3413ba42 100644 --- a/soc/espressif/esp32/soc.c +++ b/soc/espressif/esp32/soc.c @@ -137,13 +137,6 @@ void IRAM_ATTR __esp_platform_start(void) wdt_hal_disable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx); -#ifndef CONFIG_SOC_ENABLE_APPCPU - /* Configures the CPU clock, RTC slow and fast clocks, and performs - * RTC slow clock calibration. - */ - esp_clk_init(); -#endif - esp_timer_early_init(); #if CONFIG_SOC_ENABLE_APPCPU diff --git a/soc/espressif/esp32c3/Kconfig.rtc b/soc/espressif/esp32c3/Kconfig.rtc deleted file mode 100644 index b0f2e47f565..00000000000 --- a/soc/espressif/esp32c3/Kconfig.rtc +++ /dev/null @@ -1,67 +0,0 @@ -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32C3 - -choice RTC_CLK_SRC - prompt "RTC clock source" - default RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - -config RTC_CLK_SRC_INT_RC - bool "Internal 136kHz RC oscillator" - -config RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XP pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config RTC_CLK_SRC_INT_8MD256 - bool "Internal 17.5MHz oscillator, divided by 256" - -endchoice # ESP32C3_RTC_CLK_SRC - -config RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 - default 1024 if RTC_CLK_SRC_INT_RC - range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 - range 0 32766 if RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES - int "Bootstrap cycles for external 32kHz crystal" - depends on ESP_SYSTEM_RTC_EXT_XTAL - default 0 - range 0 32768 - help - To reduce the startup time of an external RTC crystal, - we bootstrap it with a 32kHz square wave for a fixed number of cycles. - Setting 0 will disable bootstrapping (if disabled, the crystal may take - longer to start up or fail to oscillate under some conditions). - - If this value is too high, a faulty crystal may initially start and then fail. - If this value is too low, an otherwise good crystal may not start. - - To accurately determine if the crystal has started, - set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000). - -endif # SOC_SERIES_ESP32C3 diff --git a/soc/espressif/esp32c3/soc.c b/soc/espressif/esp32c3/soc.c index 2e39e108705..61a4cb4c83f 100644 --- a/soc/espressif/esp32c3/soc.c +++ b/soc/espressif/esp32c3/soc.c @@ -82,11 +82,6 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) #endif /*CONFIG_SOC_FLASH_ESP32*/ - /* Configures the CPU clock, RTC slow and fast clocks, and performs - * RTC slow clock calibration. - */ - esp_clk_init(); - esp_timer_early_init(); #if CONFIG_SOC_FLASH_ESP32 diff --git a/soc/espressif/esp32s2/Kconfig.rtc b/soc/espressif/esp32s2/Kconfig.rtc deleted file mode 100644 index 61ca8d3a9df..00000000000 --- a/soc/espressif/esp32s2/Kconfig.rtc +++ /dev/null @@ -1,93 +0,0 @@ -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32S2 - -choice RTC_CLK_SRC - prompt "RTC clock source" - default RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - - "Internal 90kHz oscillator" option provides lowest deep sleep current - consumption, and does not require extra external components. However - frequency stability with respect to temperature is poor, so time may - drift in deep/light sleep modes. - - "External 32kHz crystal" provides better frequency stability, at the - expense of slightly higher (1uA) deep sleep current consumption. - - "External 32kHz oscillator" allows using 32kHz clock generated by an - external circuit. In this case, external clock signal must be connected - to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, - and <1V in case of square wave signal. Common mode voltage should be - 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. - Additionally, 1nF capacitor must be connected between 32K_XP pin and - ground. 32K_XP pin can not be used as a GPIO in this case. - - "Internal 8MHz oscillator divided by 256" option results in higher - deep sleep current (by 5uA) but has better frequency stability than - the internal 90kHz oscillator. It does not require external components. - -config RTC_CLK_SRC_INT_RC - bool "Internal 90kHz RC oscillator" - -config RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XN pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" - -endchoice - -config RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 - default 576 if RTC_CLK_SRC_INT_RC - range 0 125000 - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -config RTC_XTAL_CAL_RETRY - int "Number of attempts to repeat 32k XTAL calibration" - default 3 - depends on RTC_CLK_SRC_EXT_CRYS - help - Number of attempts to repeat 32k XTAL calibration - before giving up and switching to the internal RC. - Increase this option if the 32k crystal oscillator - does not start and switches to internal RC. - -config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES - int "Bootstrap cycles for external 32kHz crystal" - depends on ESP_SYSTEM_RTC_EXT_XTAL - default 0 - range 0 32768 - help - To reduce the startup time of an external RTC crystal, - we bootstrap it with a 32kHz square wave for a fixed number of cycles. - Setting 0 will disable bootstrapping (if disabled, the crystal may take - longer to start up or fail to oscillate under some conditions). - - If this value is too high, a faulty crystal may initially start and then fail. - If this value is too low, an otherwise good crystal may not start. - - To accurately determine if the crystal has started, - set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000). - -endif # SOC_SERIES_ESP32S2 diff --git a/soc/espressif/esp32s2/soc.c b/soc/espressif/esp32s2/soc.c index a0558bd8ea3..05913df81cf 100644 --- a/soc/espressif/esp32s2/soc.c +++ b/soc/espressif/esp32s2/soc.c @@ -129,10 +129,6 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) #endif /* CONFIG_ESP_SPIRAM */ - /* Configures the CPU clock, RTC slow and fast clocks, and performs - * RTC slow clock calibration. - */ - esp_clk_init(); esp_timer_early_init(); /* Scheduler is not started at this point. Hence, guard functions diff --git a/soc/espressif/esp32s3/Kconfig.rtc b/soc/espressif/esp32s3/Kconfig.rtc deleted file mode 100644 index 9c5d7d834ba..00000000000 --- a/soc/espressif/esp32s3/Kconfig.rtc +++ /dev/null @@ -1,63 +0,0 @@ -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32S3 - -choice RTC_CLK_SRC - prompt "RTC clock source" - default RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - config RTC_CLK_SRC_INT_RC - bool "Internal 136kHz RC oscillator" - config RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - config RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XP pin" - select ESP_SYSTEM_RTC_EXT_OSC - config RTC_CLK_SRC_INT_8MD256 - bool "Internal 17.5MHz oscillator, divided by 256" -endchoice - -config RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 - default 1024 if RTC_CLK_SRC_INT_RC - range 0 27000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 - range 0 32766 if RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES - int "Bootstrap cycles for external 32kHz crystal" - depends on ESP_SYSTEM_RTC_EXT_XTAL - default 0 - range 0 32768 - help - To reduce the startup time of an external RTC crystal, - we bootstrap it with a 32kHz square wave for a fixed number of cycles. - Setting 0 will disable bootstrapping (if disabled, the crystal may take - longer to start up or fail to oscillate under some conditions). - - If this value is too high, a faulty crystal may initially start and then fail. - If this value is too low, an otherwise good crystal may not start. - - To accurately determine if the crystal has started, - set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000). - -endif # SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s3/soc.c b/soc/espressif/esp32s3/soc.c index d8791cf6cc8..ec9d603d6cd 100644 --- a/soc/espressif/esp32s3/soc.c +++ b/soc/espressif/esp32s3/soc.c @@ -197,8 +197,6 @@ void IRAM_ATTR __esp_platform_start(void) esp_reset_reason_init(); - esp_clk_init(); - esp_timer_early_init(); #if CONFIG_SOC_ENABLE_APPCPU