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soc: lpc54114: update multi core support for LMA address offset

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Update lpc54114 support to use LMA address offset instead of linking
secondary core image into primary core memory. This will allow support
with sysbuild to be enabled. Additionally, use partitions to select where
the secondary core image will be located in flash

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-08-04 10:22:38 -05:00 • committed by Carles Cufí
commit e274fbe3f9
7 changed files with 56 additions and 27 deletions
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11
boards/arm/lpcxpresso54114/Kconfig.defconfig
View file

@ -9,4 +9,15 @@ config BOARD
default "lpcxpresso54114_m4" if BOARD_LPCXPRESSO54114_M4
default "lpcxpresso54114_m0" if BOARD_LPCXPRESSO54114_M0
# Place size restrictions on first image if dual core is enabled
if SECOND_CORE_MCUX && BOARD_LPCXPRESSO54114_M4
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
config FLASH_LOAD_SIZE
default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
endif # SECOND_CORE_MCUX && BOARD_LPCXPRESSO54114_M4
endif # BOARD_LPCXPRESSO54114_M4 || BOARD_LPCXPRESSO54114_M0

2
boards/arm/lpcxpresso54114/board.cmake
View file

@ -4,7 +4,7 @@
# SPDX-License-Identifier: Apache-2.0
#
if(CONFIG_BOARD_LPCXPRESSO54114_M4)
if(CONFIG_BOARD_LPCXPRESSO54114_M4 OR CONFIG_SECOND_CORE_MCUX)
board_runner_args(jlink "--device=LPC54114J256_M4" "--reset-after-load")
elseif(CONFIG_BOARD_LPCXPRESSO54114_M0)
board_runner_args(jlink "--device=LPC54114J256_M0" "--reset-after-load")

16
boards/arm/lpcxpresso54114/lpcxpresso54114.dtsi
View file

@ -58,3 +58,19 @@ arduino_spi: &flexcomm5 {
pinctrl-0 = <&pinmux_flexcomm5_spi>;
pinctrl-names = "default";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
slot0_partition: partition@0 {
label = "image-0";
reg = <0x00000000 0x00010000>;
};
slot1_partition: partition@10000 {
label = "image-1";
reg = <0x00010000 0x00010000>;
};
};
};

1
boards/arm/lpcxpresso54114/lpcxpresso54114_m0.dts
View file

@ -16,6 +16,7 @@
chosen {
zephyr,sram = &sram2;
zephyr,flash = &sram1;
zephyr,code-cpu1-partition = &slot1_partition;
/*zephyr,console = &flexcomm0; uncomment to use console on M0 */
/*zephyr,shell-uart = &flexcomm0; uncomment to use shell on M0 */
};

12
soc/arm/nxp_lpc/lpc54xxx/CMakeLists.txt
View file

@ -12,15 +12,3 @@ zephyr_library_include_directories(
${ZEPHYR_BASE}/kernel/include
${ZEPHYR_BASE}/arch/${ARCH}/include
)
if (CONFIG_SECOND_CORE_MCUX)
set(gen_dir ${ZEPHYR_BINARY_DIR}/include/generated/)
string(CONFIGURE ${CONFIG_SECOND_IMAGE_MCUX} core_m0_image)
add_custom_target(second_core_inc_target DEPENDS ${gen_dir}/core-m0.inc)
generate_inc_file_for_gen_target(${ZEPHYR_CURRENT_LIBRARY}
${core_m0_image}
${gen_dir}/core-m0.inc
second_core_inc_target)
endif()

20
soc/arm/nxp_lpc/lpc54xxx/Kconfig.soc
View file

@ -44,13 +44,6 @@ config SECOND_CORE_MCUX
help
Driver for second core startup
config SECOND_IMAGE_MCUX
depends on SECOND_CORE_MCUX
string "Binary image of second core's code"
help
This points to the image file for the the binary code that will be
used by the second core.
config SECOND_CORE_BOOT_ADDRESS_MCUX
depends on SECOND_CORE_MCUX
hex "Address the second core will boot at"
@ -60,4 +53,17 @@ config SECOND_CORE_BOOT_ADDRESS_MCUX
address is where we will copy the SECOND_IMAGE to. We default this to
the base of SRAM1.
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
# Move the LMA address of second core into flash
config BUILD_OUTPUT_ADJUST_LMA
depends on SECOND_CORE_MCUX && SOC_LPC54114_M0
default "-0x20010000+\
$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))"
config BUILD_OUTPUT_INFO_HEADER
default y
depends on SECOND_CORE_MCUX && SOC_LPC54114_M0
endif # SOC_SERIES_LPC54XXX

21
soc/arm/nxp_lpc/lpc54xxx/soc.c
View file

@ -27,6 +27,17 @@
#ifdef CONFIG_GPIO_MCUX_LPC
#include <fsl_pint.h>
#endif
#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC54114_M4)
#include <zephyr_image_info.h>
/* Memcpy macro to copy segments from secondary core image stored in flash
* to RAM section that secondary core boots from.
* n is the segment number, as defined in zephyr_image_info.h
*/
#define MEMCPY_SEGMENT(n, _) \
memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_ ## n) - ADJUSTED_LMA), \
(uint32_t *)(SEGMENT_LMA_ADDRESS_ ## n), \
(SEGMENT_SIZE_ ## n))
#endif
/**
*
@ -129,14 +140,10 @@ static int nxp_lpc54114_init(const struct device *arg)
SYS_INIT(nxp_lpc54114_init, PRE_KERNEL_1, 0);
#ifdef CONFIG_SECOND_CORE_MCUX
#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC54114_M4)
#define CORE_M0_BOOT_ADDRESS ((void *)CONFIG_SECOND_CORE_BOOT_ADDRESS_MCUX)
static const char core_m0[] = {
#include "core-m0.inc"
};
/**
*
* @brief Slave Init
@ -157,7 +164,7 @@ int _slave_init(const struct device *arg)
SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM2_MASK;
/* Copy second core image to SRAM */
memcpy(CORE_M0_BOOT_ADDRESS, (void *)core_m0, sizeof(core_m0));
LISTIFY(SEGMENT_NUM, MEMCPY_SEGMENT, (;));
/* Setup the reset handler pointer (PC) and stack pointer value.
* This is used once the second core runs its startup code.
@ -186,4 +193,4 @@ int _slave_init(const struct device *arg)
SYS_INIT(_slave_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif /*CONFIG_SECOND_CORE_MCUX*/
#endif /*CONFIG_SECOND_CORE_MCUX && CONFIG_SOC_LPC54114_M4 */