From e22958ceaf6020dd595ae28963e5699d5406d7bc Mon Sep 17 00:00:00 2001 From: cyliang tw Date: Mon, 11 Mar 2024 14:59:20 +0800 Subject: [PATCH] soc: nuvoton: numaker: add support for m2l31x series Add initial support for nuvoton numaker m2l31x SoC series including basic init. Signed-off-by: cyliang tw --- dts/arm/nuvoton/m2l31kid.dtsi | 23 ++ dts/arm/nuvoton/m2l31x.dtsi | 221 ++++++++++++++ .../dt-bindings/clock/numaker_m2l31x_clock.h | 274 ++++++++++++++++++ .../dt-bindings/reset/numaker_m2l31x_reset.h | 155 ++++++++++ soc/nuvoton/numaker/m2l31x/CMakeLists.txt | 9 + soc/nuvoton/numaker/m2l31x/Kconfig | 14 + soc/nuvoton/numaker/m2l31x/Kconfig.defconfig | 9 + .../numaker/m2l31x/Kconfig.defconfig.m2l31xxx | 10 + soc/nuvoton/numaker/m2l31x/Kconfig.soc | 19 ++ soc/nuvoton/numaker/m2l31x/soc.c | 86 ++++++ soc/nuvoton/numaker/m2l31x/soc.h | 13 + soc/nuvoton/numaker/soc.yml | 3 + 12 files changed, 836 insertions(+) create mode 100644 dts/arm/nuvoton/m2l31kid.dtsi create mode 100644 dts/arm/nuvoton/m2l31x.dtsi create mode 100644 include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h create mode 100644 include/zephyr/dt-bindings/reset/numaker_m2l31x_reset.h create mode 100644 soc/nuvoton/numaker/m2l31x/CMakeLists.txt create mode 100644 soc/nuvoton/numaker/m2l31x/Kconfig create mode 100644 soc/nuvoton/numaker/m2l31x/Kconfig.defconfig create mode 100644 soc/nuvoton/numaker/m2l31x/Kconfig.defconfig.m2l31xxx create mode 100644 soc/nuvoton/numaker/m2l31x/Kconfig.soc create mode 100644 soc/nuvoton/numaker/m2l31x/soc.c create mode 100644 soc/nuvoton/numaker/m2l31x/soc.h diff --git a/dts/arm/nuvoton/m2l31kid.dtsi b/dts/arm/nuvoton/m2l31kid.dtsi new file mode 100644 index 00000000000..32c793ded8c --- /dev/null +++ b/dts/arm/nuvoton/m2l31kid.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(168)>; + }; + + soc { + rmc: flash-controller@4000c000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(512)>; + }; + }; + }; +}; diff --git a/dts/arm/nuvoton/m2l31x.dtsi b/dts/arm/nuvoton/m2l31x.dtsi new file mode 100644 index 00000000000..00af64b124c --- /dev/null +++ b/dts/arm/nuvoton/m2l31x.dtsi @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +/ { + chosen { + zephyr,flash-controller = &rmc; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m23"; + reg = <0>; + }; + }; + + sysclk: system-clock { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + }; + + soc { + scc: system-clock-controller@40000200 { + compatible = "nuvoton,numaker-scc"; + reg = <0x40000200 0x100>; + #clock-cells = <0>; + clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 | + NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2)>; + core-clock = ; + + pcc: peripheral-clock-controller { + compatible = "nuvoton,numaker-pcc"; + #clock-cells = <3>; + }; + }; + + rst: reset-controller@40000000 { + compatible = "nuvoton,numaker-rst"; + reg = <0x40000000 0x20>; + #reset-cells = <1>; + }; + + rmc: flash-controller@4000c000 { + compatible = "nuvoton,numaker-rmc"; + reg = <0x4000c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + erase-block-size = <4096>; + write-block-size = <4>; + }; + }; + + uart0: serial@40070000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40070000 0x1000>; + interrupts = <36 0>; + resets = <&rst NUMAKER_UART0_RST>; + clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_CLKSEL4_UART0SEL_HIRC + NUMAKER_CLK_CLKDIV0_UART0(1)>; + status = "disabled"; + }; + + uart1: serial@40071000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40071000 0x1000>; + interrupts = <37 0>; + resets = <&rst NUMAKER_UART1_RST>; + clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_CLKSEL4_UART1SEL_HIRC + NUMAKER_CLK_CLKDIV0_UART1(1)>; + status = "disabled"; + }; + + uart2: serial@40072000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40072000 0x1000>; + interrupts = <48 0>; + resets = <&rst NUMAKER_UART2_RST>; + clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_CLKSEL4_UART2SEL_HIRC + NUMAKER_CLK_CLKDIV4_UART2(1)>; + status = "disabled"; + }; + + uart3: serial@40073000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40073000 0x1000>; + interrupts = <49 0>; + resets = <&rst NUMAKER_UART3_RST>; + clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_CLKSEL4_UART3SEL_HIRC + NUMAKER_CLK_CLKDIV4_UART3(1)>; + status = "disabled"; + }; + + uart4: serial@40074000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40074000 0x1000>; + interrupts = <74 0>; + resets = <&rst NUMAKER_UART4_RST>; + clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_CLKSEL4_UART4SEL_HIRC + NUMAKER_CLK_CLKDIV4_UART4(1)>; + status = "disabled"; + }; + + uart5: serial@40075000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40075000 0x1000>; + interrupts = <75 0>; + resets = <&rst NUMAKER_UART5_RST>; + clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_CLKSEL4_UART5SEL_HIRC + NUMAKER_CLK_CLKDIV4_UART5(1)>; + status = "disabled"; + }; + + uart6: serial@40076000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40076000 0x1000>; + interrupts = <102 0>; + resets = <&rst NUMAKER_UART6_RST>; + clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_CLKSEL4_UART6SEL_HIRC + NUMAKER_CLK_CLKDIV4_UART6(1)>; + status = "disabled"; + }; + + uart7: serial@40077000 { + compatible = "nuvoton,numaker-uart"; + reg = <0x40077000 0x1000>; + interrupts = <103 0>; + resets = <&rst NUMAKER_UART7_RST>; + clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_CLKSEL4_UART7SEL_HIRC + NUMAKER_CLK_CLKDIV4_UART7(1)>; + status = "disabled"; + }; + + pinctrl: pin-controller@40000080 { + compatible = "nuvoton,numaker-pinctrl"; + reg = <0x40000080 0x20 + 0x40000500 0x80>; + reg-names = "mfos", "mfp"; + }; + + gpioa: gpio@40004000 { + compatible = "nuvoton,numaker-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40004000 0x40>; + clocks = <&pcc NUMAKER_GPA_MODULE 0 0>; + status = "disabled"; + interrupts = <16 2>; + }; + + gpiob: gpio@40004040 { + compatible = "nuvoton,numaker-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40004040 0x40>; + clocks = <&pcc NUMAKER_GPB_MODULE 0 0>; + status = "disabled"; + interrupts = <17 2>; + }; + + gpioc: gpio@40004080 { + compatible = "nuvoton,numaker-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40004080 0x40>; + clocks = <&pcc NUMAKER_GPC_MODULE 0 0>; + status = "disabled"; + interrupts = <18 2>; + }; + + gpiod: gpio@400040c0 { + compatible = "nuvoton,numaker-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x400040c0 0x40>; + clocks = <&pcc NUMAKER_GPD_MODULE 0 0>; + status = "disabled"; + interrupts = <19 2>; + }; + + gpioe: gpio@40004100 { + compatible = "nuvoton,numaker-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40004100 0x40>; + clocks = <&pcc NUMAKER_GPE_MODULE 0 0>; + status = "disabled"; + interrupts = <20 2>; + }; + + gpiof: gpio@40004140 { + compatible = "nuvoton,numaker-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x40004140 0x40>; + clocks = <&pcc NUMAKER_GPF_MODULE 0 0>; + status = "disabled"; + interrupts = <21 2>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <2>; +}; diff --git a/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h b/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h new file mode 100644 index 00000000000..fab7f656e4f --- /dev/null +++ b/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M2L31_CLOCK_H +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M2L31_CLOCK_H + +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_LXT 0x00000001 +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_PLL 0x00000002 +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_LIRC 0x00000003 +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_MIRC 0x00000005 +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_HIRC48M 0x00000006 +#define NUMAKER_CLK_CLKSEL0_HCLKSEL_HIRC 0x00000007 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_LXT 0x00000001 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_PLL 0x00000002 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_LIRC 0x00000003 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_MIRC 0x00000005 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_HIRC48M 0x00000006 +#define NUMAKER_CLK_CLKSEL0_HCLK0SEL_HIRC 0x00000007 +#define NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL0_STCLKSEL_LXT 0x00000008 +#define NUMAKER_CLK_CLKSEL0_STCLKSEL_HXT_DIV2 0x00000010 +#define NUMAKER_CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x00000018 +#define NUMAKER_CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x00000038 +#define NUMAKER_CLK_CLKSEL0_HCLK1SEL_HIRC 0x00000000 +#define NUMAKER_CLK_CLKSEL0_HCLK1SEL_MIRC 0x00001000 +#define NUMAKER_CLK_CLKSEL0_HCLK1SEL_LXT 0x00002000 +#define NUMAKER_CLK_CLKSEL0_HCLK1SEL_LIRC 0x00003000 +#define NUMAKER_CLK_CLKSEL0_HCLK1SEL_HIRC48M_DIV2 0x00004000 +#define NUMAKER_CLK_CLKSEL0_USBSEL_HIRC48M 0x00000000 +#define NUMAKER_CLK_CLKSEL0_USBSEL_PLL 0x00000100 +#define NUMAKER_CLK_CLKSEL0_EADC0SEL_PLL 0x00000400 +#define NUMAKER_CLK_CLKSEL0_EADC0SEL_HCLK 0x00000800 +#define NUMAKER_CLK_CLKSEL0_EADC0SEL_HCLK0 0x00000800 +#define NUMAKER_CLK_CLKSEL0_EADC0SEL_HIRC 0x00000C00 +#define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HIRC48M 0x01000000 +#define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HCLK 0x02000000 +#define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HCLK0 0x02000000 +#define NUMAKER_CLK_CLKSEL0_CANFD0SEL_HIRC 0x03000000 +#define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HIRC48M 0x04000000 +#define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HCLK 0x08000000 +#define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HCLK0 0x08000000 +#define NUMAKER_CLK_CLKSEL0_CANFD1SEL_HIRC 0x0C000000 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_LXT 0x00000010 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_HCLK 0x00000020 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_HCLK0 0x00000020 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_HIRC 0x00000030 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_LIRC 0x00000040 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_HIRC48M 0x00000050 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_PLL 0x00000060 +#define NUMAKER_CLK_CLKSEL1_CLKOSEL_MIRC 0x00000070 +#define NUMAKER_CLK_CLKSEL1_TMR0SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL1_TMR0SEL_LXT 0x00000100 +#define NUMAKER_CLK_CLKSEL1_TMR0SEL_PCLK0 0x00000200 +#define NUMAKER_CLK_CLKSEL1_TMR0SEL_EXT 0x00000300 +#define NUMAKER_CLK_CLKSEL1_TMR0SEL_LIRC 0x00000500 +#define NUMAKER_CLK_CLKSEL1_TMR0SEL_HIRC 0x00000700 +#define NUMAKER_CLK_CLKSEL1_TMR1SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL1_TMR1SEL_LXT 0x00001000 +#define NUMAKER_CLK_CLKSEL1_TMR1SEL_PCLK0 0x00002000 +#define NUMAKER_CLK_CLKSEL1_TMR1SEL_EXT 0x00003000 +#define NUMAKER_CLK_CLKSEL1_TMR1SEL_LIRC 0x00005000 +#define NUMAKER_CLK_CLKSEL1_TMR1SEL_HIRC 0x00007000 +#define NUMAKER_CLK_CLKSEL1_TMR2SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL1_TMR2SEL_LXT 0x00010000 +#define NUMAKER_CLK_CLKSEL1_TMR2SEL_PCLK1 0x00020000 +#define NUMAKER_CLK_CLKSEL1_TMR2SEL_EXT 0x00030000 +#define NUMAKER_CLK_CLKSEL1_TMR2SEL_LIRC 0x00050000 +#define NUMAKER_CLK_CLKSEL1_TMR2SEL_HIRC 0x00070000 +#define NUMAKER_CLK_CLKSEL1_TMR3SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL1_TMR3SEL_LXT 0x00100000 +#define NUMAKER_CLK_CLKSEL1_TMR3SEL_PCLK1 0x00200000 +#define NUMAKER_CLK_CLKSEL1_TMR3SEL_EXT 0x00300000 +#define NUMAKER_CLK_CLKSEL1_TMR3SEL_LIRC 0x00500000 +#define NUMAKER_CLK_CLKSEL1_TMR3SEL_HIRC 0x00700000 +#define NUMAKER_CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 0x80000000 +#define NUMAKER_CLK_CLKSEL1_WWDTSEL_HCLK0_DIV2048 0x80000000 +#define NUMAKER_CLK_CLKSEL1_WWDTSEL_LIRC 0xC0000000 +#define NUMAKER_CLK_CLKSEL2_EPWM0SEL_HCLK 0x00000000 +#define NUMAKER_CLK_CLKSEL2_EPWM0SEL_HCLK0 0x00000000 +#define NUMAKER_CLK_CLKSEL2_EPWM0SEL_PCLK0 0x00000001 +#define NUMAKER_CLK_CLKSEL2_EPWM1SEL_HCLK 0x00000000 +#define NUMAKER_CLK_CLKSEL2_EPWM1SEL_HCLK0 0x00000000 +#define NUMAKER_CLK_CLKSEL2_EPWM1SEL_PCLK1 0x00000002 +#define NUMAKER_CLK_CLKSEL2_QSPI0SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL2_QSPI0SEL_PLL 0x00000004 +#define NUMAKER_CLK_CLKSEL2_QSPI0SEL_PCLK0 0x00000008 +#define NUMAKER_CLK_CLKSEL2_QSPI0SEL_HIRC 0x0000000C +#define NUMAKER_CLK_CLKSEL2_SPI0SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL2_SPI0SEL_PLL 0x00000010 +#define NUMAKER_CLK_CLKSEL2_SPI0SEL_PCLK1 0x00000020 +#define NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC 0x00000030 +#define NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC48M 0x00000040 +#define NUMAKER_CLK_CLKSEL2_TKSEL_HIRC 0x00000000 +#define NUMAKER_CLK_CLKSEL2_TKSEL_MIRC 0x00000080 +#define NUMAKER_CLK_CLKSEL2_SPI1SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL2_SPI1SEL_PLL 0x00001000 +#define NUMAKER_CLK_CLKSEL2_SPI1SEL_PCLK0 0x00002000 +#define NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC 0x00003000 +#define NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC48M 0x00004000 +#define NUMAKER_CLK_CLKSEL3_PWM0SEL_HCLK 0x00000000 +#define NUMAKER_CLK_CLKSEL3_PWM0SEL_HCLK0 0x00000000 +#define NUMAKER_CLK_CLKSEL3_PWM0SEL_PCLK0 0x00000040 +#define NUMAKER_CLK_CLKSEL3_PWM1SEL_HCLK 0x00000000 +#define NUMAKER_CLK_CLKSEL3_PWM1SEL_HCLK0 0x00000000 +#define NUMAKER_CLK_CLKSEL3_PWM1SEL_PCLK1 0x00000080 +#define NUMAKER_CLK_CLKSEL3_SPI2SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL3_SPI2SEL_PLL 0x00000100 +#define NUMAKER_CLK_CLKSEL3_SPI2SEL_PCLK1 0x00000200 +#define NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC 0x00000300 +#define NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC48M 0x00000400 +#define NUMAKER_CLK_CLKSEL3_SPI3SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL3_SPI3SEL_PLL 0x00001000 +#define NUMAKER_CLK_CLKSEL3_SPI3SEL_PCLK0 0x00002000 +#define NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC 0x00003000 +#define NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC48M 0x00004000 +#define NUMAKER_CLK_CLKSEL4_UART0SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART0SEL_PLL 0x00000001 +#define NUMAKER_CLK_CLKSEL4_UART0SEL_LXT 0x00000002 +#define NUMAKER_CLK_CLKSEL4_UART0SEL_HIRC 0x00000003 +#define NUMAKER_CLK_CLKSEL4_UART0SEL_MIRC 0x00000004 +#define NUMAKER_CLK_CLKSEL4_UART0SEL_HIRC48M 0x00000005 +#define NUMAKER_CLK_CLKSEL4_UART1SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART1SEL_PLL 0x00000010 +#define NUMAKER_CLK_CLKSEL4_UART1SEL_LXT 0x00000020 +#define NUMAKER_CLK_CLKSEL4_UART1SEL_HIRC 0x00000030 +#define NUMAKER_CLK_CLKSEL4_UART1SEL_MIRC 0x00000040 +#define NUMAKER_CLK_CLKSEL4_UART1SEL_HIRC48M 0x00000050 +#define NUMAKER_CLK_CLKSEL4_UART2SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART2SEL_PLL 0x00000100 +#define NUMAKER_CLK_CLKSEL4_UART2SEL_LXT 0x00000200 +#define NUMAKER_CLK_CLKSEL4_UART2SEL_HIRC 0x00000300 +#define NUMAKER_CLK_CLKSEL4_UART2SEL_MIRC 0x00000400 +#define NUMAKER_CLK_CLKSEL4_UART2SEL_HIRC48M 0x00000500 +#define NUMAKER_CLK_CLKSEL4_UART3SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART3SEL_PLL 0x00001000 +#define NUMAKER_CLK_CLKSEL4_UART3SEL_LXT 0x00002000 +#define NUMAKER_CLK_CLKSEL4_UART3SEL_HIRC 0x00003000 +#define NUMAKER_CLK_CLKSEL4_UART3SEL_MIRC 0x00004000 +#define NUMAKER_CLK_CLKSEL4_UART3SEL_HIRC48M 0x00005000 +#define NUMAKER_CLK_CLKSEL4_UART4SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART4SEL_PLL 0x00010000 +#define NUMAKER_CLK_CLKSEL4_UART4SEL_LXT 0x00020000 +#define NUMAKER_CLK_CLKSEL4_UART4SEL_HIRC 0x00030000 +#define NUMAKER_CLK_CLKSEL4_UART4SEL_MIRC 0x00040000 +#define NUMAKER_CLK_CLKSEL4_UART4SEL_HIRC48M 0x00050000 +#define NUMAKER_CLK_CLKSEL4_UART5SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART5SEL_PLL 0x00100000 +#define NUMAKER_CLK_CLKSEL4_UART5SEL_LXT 0x00200000 +#define NUMAKER_CLK_CLKSEL4_UART5SEL_HIRC 0x00300000 +#define NUMAKER_CLK_CLKSEL4_UART5SEL_MIRC 0x00400000 +#define NUMAKER_CLK_CLKSEL4_UART5SEL_HIRC48M 0x00500000 +#define NUMAKER_CLK_CLKSEL4_UART6SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART6SEL_PLL 0x01000000 +#define NUMAKER_CLK_CLKSEL4_UART6SEL_LXT 0x02000000 +#define NUMAKER_CLK_CLKSEL4_UART6SEL_HIRC 0x03000000 +#define NUMAKER_CLK_CLKSEL4_UART6SEL_MIRC 0x04000000 +#define NUMAKER_CLK_CLKSEL4_UART6SEL_HIRC48M 0x05000000 +#define NUMAKER_CLK_CLKSEL4_UART7SEL_HXT 0x00000000 +#define NUMAKER_CLK_CLKSEL4_UART7SEL_PLL 0x10000000 +#define NUMAKER_CLK_CLKSEL4_UART7SEL_LXT 0x20000000 +#define NUMAKER_CLK_CLKSEL4_UART7SEL_HIRC 0x30000000 +#define NUMAKER_CLK_CLKSEL4_UART7SEL_MIRC 0x40000000 +#define NUMAKER_CLK_CLKSEL4_UART7SEL_HIRC48M 0x50000000 +#define NUMAKER_CLK_CLKDIV0_HCLK(x) (((x) - 1UL) << (0)) +#define NUMAKER_CLK_CLKDIV0_HCLK0(x) (((x) - 1UL) << (0)) +#define NUMAKER_CLK_CLKDIV0_USB(x) (((x) - 1UL) << (4)) +#define NUMAKER_CLK_CLKDIV0_UART0(x) (((x) - 1UL) << (8)) +#define NUMAKER_CLK_CLKDIV0_UART1(x) (((x) - 1UL) << (12)) +#define NUMAKER_CLK_CLKDIV0_EADC0(x) (((x) - 1UL) << (16)) +#define NUMAKER_CLK_CLKDIV4_UART2(x) (((x) - 1UL) << (0)) +#define NUMAKER_CLK_CLKDIV4_UART3(x) (((x) - 1UL) << (4)) +#define NUMAKER_CLK_CLKDIV4_UART4(x) (((x) - 1UL) << (8)) +#define NUMAKER_CLK_CLKDIV4_UART5(x) (((x) - 1UL) << (12)) +#define NUMAKER_CLK_CLKDIV4_UART6(x) (((x) - 1UL) << (16)) +#define NUMAKER_CLK_CLKDIV4_UART7(x) (((x) - 1UL) << (20)) +#define NUMAKER_CLK_CLKDIV5_CANFD0(x) (((x) - 1UL) << (0)) +#define NUMAKER_CLK_CLKDIV5_CANFD1(x) (((x) - 1UL) << (4)) +#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV1 0x00000000 +#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 0x00000001 +#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV4 0x00000002 +#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV8 0x00000003 +#define NUMAKER_CLK_PCLKDIV_APB0DIV_DIV16 0x00000004 +#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV1 0x00000000 +#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2 0x00000010 +#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV4 0x00000020 +#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV8 0x00000030 +#define NUMAKER_CLK_PCLKDIV_APB1DIV_DIV16 0x00000040 +#define NUMAKER_PDMA0_MODULE 0x00000001 +#define NUMAKER_ISP_MODULE 0x00000002 +#define NUMAKER_EBI_MODULE 0x00000003 +#define NUMAKER_ST_MODULE 0x018C0004 +#define NUMAKER_CRC_MODULE 0x00000007 +#define NUMAKER_CRPT_MODULE 0x0000000C +#define NUMAKER_KS_MODULE 0x0000000D +#define NUMAKER_USBH_MODULE 0x00A01090 +#define NUMAKER_GPA_MODULE 0x00000018 +#define NUMAKER_GPB_MODULE 0x00000019 +#define NUMAKER_GPC_MODULE 0x0000001A +#define NUMAKER_GPD_MODULE 0x0000001B +#define NUMAKER_GPE_MODULE 0x0000001C +#define NUMAKER_GPF_MODULE 0x0000001D +#define NUMAKER_GPG_MODULE 0x0000001E +#define NUMAKER_GPH_MODULE 0x0000001F +#define NUMAKER_RTC_MODULE 0x20000001 +#define NUMAKER_TMR0_MODULE 0x25A00002 +#define NUMAKER_TMR1_MODULE 0x25B00003 +#define NUMAKER_TMR2_MODULE 0x25C00004 +#define NUMAKER_TMR3_MODULE 0x25D00005 +#define NUMAKER_CLKO_MODULE 0x26100006 +#define NUMAKER_ACMP01_MODULE 0x20000007 +#define NUMAKER_I2C0_MODULE 0x20000008 +#define NUMAKER_I2C1_MODULE 0x20000009 +#define NUMAKER_I2C2_MODULE 0x2000000A +#define NUMAKER_I2C3_MODULE 0x2000000B +#define NUMAKER_QSPI0_MODULE 0x2908000C +#define NUMAKER_SPI0_MODULE 0x2990000D +#define NUMAKER_SPI1_MODULE 0x29B0000E +#define NUMAKER_SPI2_MODULE 0x2DA0000F +#define NUMAKER_UART0_MODULE 0x31801110 +#define NUMAKER_UART1_MODULE 0x31901191 +#define NUMAKER_UART2_MODULE 0x31A11012 +#define NUMAKER_UART3_MODULE 0x31B11093 +#define NUMAKER_UART4_MODULE 0x31C11114 +#define NUMAKER_UART5_MODULE 0x31D11195 +#define NUMAKER_UART6_MODULE 0x31E11216 +#define NUMAKER_UART7_MODULE 0x31F11297 +#define NUMAKER_OTG_MODULE 0x2000001A +#define NUMAKER_USBD_MODULE 0x20A0109B +#define NUMAKER_EADC0_MODULE 0x2128221C +#define NUMAKER_TRNG_MODULE 0x2000001F +#define NUMAKER_SPI3_MODULE 0x4DB00006 +#define NUMAKER_USCI0_MODULE 0x40000008 +#define NUMAKER_USCI1_MODULE 0x40000009 +#define NUMAKER_WWDT_MODULE 0x4578000B +#define NUMAKER_DAC_MODULE 0x4000000C +#define NUMAKER_EPWM0_MODULE 0x48800010 +#define NUMAKER_EPWM1_MODULE 0x48840011 +#define NUMAKER_EQEI0_MODULE 0x40000016 +#define NUMAKER_EQEI1_MODULE 0x40000017 +#define NUMAKER_TK_MODULE 0x489C0019 +#define NUMAKER_ECAP0_MODULE 0x4000001A +#define NUMAKER_ECAP1_MODULE 0x4000001B +#define NUMAKER_ACMP2_MODULE 0x60000007 +#define NUMAKER_PWM0_MODULE 0x6C980008 +#define NUMAKER_PWM1_MODULE 0x6C9C0009 +#define NUMAKER_UTCPD0_MODULE 0x6000000F +#define NUMAKER_CANRAM0_MODULE 0x80000010 +#define NUMAKER_CANRAM1_MODULE 0x80000011 +#define NUMAKER_CANFD0_MODULE 0x81621014 +#define NUMAKER_CANFD1_MODULE 0x816A1095 +#define NUMAKER_HCLK1_MODULE 0x81B3101C +#define NUMAKER_LPPDMA0_MODULE 0xA0000000 +#define NUMAKER_LPGPIO_MODULE 0xA0000001 +#define NUMAKER_LPSRAM_MODULE 0xA0000002 +#define NUMAKER_WDT_MODULE 0xB5600010 +#define NUMAKER_LPSPI0_MODULE 0xB5080011 +#define NUMAKER_LPI2C0_MODULE 0xA0000012 +#define NUMAKER_LPUART0_MODULE 0xB5031113 +#define NUMAKER_LPTMR0_MODULE 0xB5A00014 +#define NUMAKER_LPTMR1_MODULE 0xB5B00015 +#define NUMAKER_TTMR0_MODULE 0xB5100016 +#define NUMAKER_TTMR1_MODULE 0xB5180017 +#define NUMAKER_LPADC0_MODULE 0xB5431218 +#define NUMAKER_OPA_MODULE 0xA000001B + +#endif diff --git a/include/zephyr/dt-bindings/reset/numaker_m2l31x_reset.h b/include/zephyr/dt-bindings/reset/numaker_m2l31x_reset.h new file mode 100644 index 00000000000..8c41ab4bea7 --- /dev/null +++ b/include/zephyr/dt-bindings/reset/numaker_m2l31x_reset.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M2L31X_RESET_H +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M2L31X_RESET_H + +/* Beginning of M2L31 BSP sys_reg.h reset module copy */ + +#define LPSCC_IPRST0_LPPDMA0RST_Pos 0 +#define LPSCC_IPRST0_LPGPIORST_Pos 1 +#define LPSCC_IPRST0_LPSRAMRST_Pos 2 +#define LPSCC_IPRST0_WDTRST_Pos 16 +#define LPSCC_IPRST0_LPSPI0RST_Pos 17 +#define LPSCC_IPRST0_LPI2C0RST_Pos 18 +#define LPSCC_IPRST0_LPUART0RST_Pos 19 +#define LPSCC_IPRST0_LPTMR0RST_Pos 20 +#define LPSCC_IPRST0_LPTMR1RST_Pos 21 +#define LPSCC_IPRST0_TTMR0RST_Pos 22 +#define LPSCC_IPRST0_TTMR1RST_Pos 23 +#define LPSCC_IPRST0_LPADC0RST_Pos 24 +#define LPSCC_IPRST0_OPARST_Pos 27 +#define SYS_IPRST0_CHIPRST_Pos 0 +#define SYS_IPRST0_CPURST_Pos 1 +#define SYS_IPRST0_PDMA0RST_Pos 2 +#define SYS_IPRST0_EBIRST_Pos 3 +#define SYS_IPRST0_USBHRST_Pos 4 +#define SYS_IPRST0_CRCRST_Pos 7 +#define SYS_IPRST0_CRPTRST_Pos 12 +#define SYS_IPRST0_CANFD0RST_Pos 20 +#define SYS_IPRST0_CANFD1RST_Pos 21 +#define SYS_IPRST1_GPIORST_Pos 1 +#define SYS_IPRST1_TMR0RST_Pos 2 +#define SYS_IPRST1_TMR1RST_Pos 3 +#define SYS_IPRST1_TMR2RST_Pos 4 +#define SYS_IPRST1_TMR3RST_Pos 5 +#define SYS_IPRST1_ACMP01RST_Pos 7 +#define SYS_IPRST1_I2C0RST_Pos 8 +#define SYS_IPRST1_I2C1RST_Pos 9 +#define SYS_IPRST1_I2C2RST_Pos 10 +#define SYS_IPRST1_I2C3RST_Pos 11 +#define SYS_IPRST1_QSPI0RST_Pos 12 +#define SYS_IPRST1_SPI0RST_Pos 13 +#define SYS_IPRST1_SPI1RST_Pos 14 +#define SYS_IPRST1_SPI2RST_Pos 15 +#define SYS_IPRST1_UART0RST_Pos 16 +#define SYS_IPRST1_UART1RST_Pos 17 +#define SYS_IPRST1_UART2RST_Pos 18 +#define SYS_IPRST1_UART3RST_Pos 19 +#define SYS_IPRST1_UART4RST_Pos 20 +#define SYS_IPRST1_UART5RST_Pos 21 +#define SYS_IPRST1_UART6RST_Pos 22 +#define SYS_IPRST1_UART7RST_Pos 23 +#define SYS_IPRST1_OTGRST_Pos 26 +#define SYS_IPRST1_USBDRST_Pos 27 +#define SYS_IPRST1_EADC0RST_Pos 28 +#define SYS_IPRST1_TRNGRST_Pos 31 +#define SYS_IPRST2_SPI3RST_Pos 6 +#define SYS_IPRST2_USCI0RST_Pos 8 +#define SYS_IPRST2_USCI1RST_Pos 9 +#define SYS_IPRST2_WWDTRST_Pos 11 +#define SYS_IPRST2_DACRST_Pos 12 +#define SYS_IPRST2_EPWM0RST_Pos 16 +#define SYS_IPRST2_EPWM1RST_Pos 17 +#define SYS_IPRST2_EQEI0RST_Pos 22 +#define SYS_IPRST2_EQEI1RST_Pos 23 +#define SYS_IPRST2_TKRST_Pos 25 +#define SYS_IPRST2_ECAP0RST_Pos 26 +#define SYS_IPRST2_ECAP1RST_Pos 27 +#define SYS_IPRST3_ACMP2RST_Pos 7 +#define SYS_IPRST3_PWM0RST_Pos 8 +#define SYS_IPRST3_PWM1RST_Pos 9 +#define SYS_IPRST3_UTCPD0RST_Pos 15 + +/* End of M2L31 BSP sys_reg.h reset module copy */ + +/* Beginning of M2L31 BSP sys.h reset module copy */ + +/*--------------------------------------------------------------------- + * Module Reset Control Resister constant definitions. + *--------------------------------------------------------------------- + */ + +#define NUMAKER_PDMA0_RST ((0UL<<24) | SYS_IPRST0_PDMA0RST_Pos) +#define NUMAKER_EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos) +#define NUMAKER_USBH_RST ((0UL<<24) | SYS_IPRST0_USBHRST_Pos) +#define NUMAKER_CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos) +#define NUMAKER_CRPT_RST ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos) +#define NUMAKER_CANFD0_RST ((0UL<<24) | SYS_IPRST0_CANFD0RST_Pos) +#define NUMAKER_CANFD1_RST ((0UL<<24) | SYS_IPRST0_CANFD1RST_Pos) + +#define NUMAKER_GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos) +#define NUMAKER_TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos) +#define NUMAKER_TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos) +#define NUMAKER_TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos) +#define NUMAKER_TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos) +#define NUMAKER_ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos) +#define NUMAKER_I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos) +#define NUMAKER_I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos) +#define NUMAKER_I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos) +#define NUMAKER_I2C3_RST ((4UL<<24) | SYS_IPRST1_I2C3RST_Pos) +#define NUMAKER_QSPI0_RST ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos) +#define NUMAKER_SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos) +#define NUMAKER_SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos) +#define NUMAKER_SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos) +#define NUMAKER_UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos) +#define NUMAKER_UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos) +#define NUMAKER_UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos) +#define NUMAKER_UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos) +#define NUMAKER_UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos) +#define NUMAKER_UART5_RST ((4UL<<24) | SYS_IPRST1_UART5RST_Pos) +#define NUMAKER_UART6_RST ((4UL<<24) | SYS_IPRST1_UART6RST_Pos) +#define NUMAKER_UART7_RST ((4UL<<24) | SYS_IPRST1_UART7RST_Pos) +#define NUMAKER_OTG_RST ((4UL<<24) | SYS_IPRST1_OTGRST_Pos) +#define NUMAKER_USBD_RST ((4UL<<24) | SYS_IPRST1_USBDRST_Pos) +#define NUMAKER_EADC0_RST ((4UL<<24) | SYS_IPRST1_EADC0RST_Pos) +#define NUMAKER_TRNG_RST ((4UL<<24) | SYS_IPRST1_TRNGRST_Pos) + +#define NUMAKER_SPI3_RST ((8UL<<24) | SYS_IPRST2_SPI3RST_Pos) +#define NUMAKER_USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos) +#define NUMAKER_USCI1_RST ((8UL<<24) | SYS_IPRST2_USCI1RST_Pos) +#define NUMAKER_WWDT_RST ((8UL<<24) | SYS_IPRST2_WWDTRST_Pos) +#define NUMAKER_DAC_RST ((8UL<<24) | SYS_IPRST2_DACRST_Pos) +#define NUMAKER_EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos) +#define NUMAKER_EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos) +#define NUMAKER_EQEI0_RST ((8UL<<24) | SYS_IPRST2_EQEI0RST_Pos) +#define NUMAKER_EQEI1_RST ((8UL<<24) | SYS_IPRST2_EQEI1RST_Pos) +#define NUMAKER_TK_RST ((8UL<<24) | SYS_IPRST2_TKRST_Pos) +#define NUMAKER_ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos) +#define NUMAKER_ECAP1_RST ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos) + +#define NUMAKER_ACMP2_RST ((0x18UL<<24) | SYS_IPRST3_ACMP2RST_Pos) +#define NUMAKER_PWM0_RST ((0x18UL<<24) | SYS_IPRST3_PWM0RST_Pos) +#define NUMAKER_PWM1_RST ((0x18UL<<24) | SYS_IPRST3_PWM1RST_Pos) +#define NUMAKER_UTCPD0_RST ((0x18UL<<24) | SYS_IPRST3_UTCPD0RST_Pos) + +#define NUMAKER_LPPDMA0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPPDMA0RST_Pos) +#define NUMAKER_LPGPIO_RST ((0x80UL<<24) | LPSCC_IPRST0_LPGPIORST_Pos) +#define NUMAKER_LPSRAM_RST ((0x80UL<<24) | LPSCC_IPRST0_LPSRAMRST_Pos) +#define NUMAKER_WDT_RST ((0x80UL<<24) | LPSCC_IPRST0_WDTRST_Pos) +#define NUMAKER_LPSPI0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPSPI0RST_Pos) +#define NUMAKER_LPI2C0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPI2C0RST_Pos) +#define NUMAKER_LPUART0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPUART0RST_Pos) +#define NUMAKER_LPTMR0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPTMR0RST_Pos) +#define NUMAKER_LPTMR1_RST ((0x80UL<<24) | LPSCC_IPRST0_LPTMR1RST_Pos) +#define NUMAKER_TTMR0_RST ((0x80UL<<24) | LPSCC_IPRST0_TTMR0RST_Pos) +#define NUMAKER_TTMR1_RST ((0x80UL<<24) | LPSCC_IPRST0_TTMR1RST_Pos) +#define NUMAKER_LPADC0_RST ((0x80UL<<24) | LPSCC_IPRST0_LPADC0RST_Pos) +#define NUMAKER_OPA_RST ((0x80UL<<24) | LPSCC_IPRST0_OPARST_Pos) + +/* End of M2L31 BSP sys.h reset module copy */ + +#endif diff --git a/soc/nuvoton/numaker/m2l31x/CMakeLists.txt b/soc/nuvoton/numaker/m2l31x/CMakeLists.txt new file mode 100644 index 00000000000..c1295bf59ad --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nuvoton/numaker/m2l31x/Kconfig b/soc/nuvoton/numaker/m2l31x/Kconfig new file mode 100644 index 00000000000..04b7eba5765 --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_M2L31X + select ARM + select CPU_CORTEX_M23 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_DWT + select CPU_CORTEX_M_HAS_VTOR + select CPU_HAS_ARM_MPU + +config SOC_M2L31XXX + select HAS_NUMAKER_HAL diff --git a/soc/nuvoton/numaker/m2l31x/Kconfig.defconfig b/soc/nuvoton/numaker/m2l31x/Kconfig.defconfig new file mode 100644 index 00000000000..906b3b02dc3 --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_M2L31X + +rsource "Kconfig.defconfig.m2l31*" + +endif # SOC_SERIES_M2L31X diff --git a/soc/nuvoton/numaker/m2l31x/Kconfig.defconfig.m2l31xxx b/soc/nuvoton/numaker/m2l31x/Kconfig.defconfig.m2l31xxx new file mode 100644 index 00000000000..42160f9e8ce --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/Kconfig.defconfig.m2l31xxx @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_M2L31XXX + +config NUM_IRQS + default 143 + +endif # SOC_M2L31XXX diff --git a/soc/nuvoton/numaker/m2l31x/Kconfig.soc b/soc/nuvoton/numaker/m2l31x/Kconfig.soc new file mode 100644 index 00000000000..c9ce4c857c5 --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/Kconfig.soc @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_M2L31X + bool + select SOC_FAMILY_NUMAKER + help + Enable support for Nuvoton M2L31X MCU series + +config SOC_M2L31XXX + bool + select SOC_SERIES_M2L31X + +config SOC_SERIES + default "m2l31x" if SOC_SERIES_M2L31X + +config SOC + default "m2l31xxx" if SOC_M2L31XXX diff --git a/soc/nuvoton/numaker/m2l31x/soc.c b/soc/nuvoton/numaker/m2l31x/soc.c new file mode 100644 index 00000000000..e766b27cda9 --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/soc.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +/* Hardware and starter kit includes. */ +#include + +void z_arm_platform_init(void) +{ + SystemInit(); + + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* + * ------------------- + * Init System Clock + * ------------------- + */ + +#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hxt) + /* Enable/disable 4~24 MHz external crystal oscillator (HXT) */ + if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_ENABLE) { + CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + } else if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_DISABLE) { + CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk); + } +#endif + +#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), lxt) + /* Enable/disable 32.768 kHz low-speed external crystal oscillator (LXT) */ + if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_ENABLE) { + CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk); + /* Wait for LXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk); + } else if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_DISABLE) { + CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk); + } +#endif + + /* Enable 12 MHz high-speed internal RC oscillator (HIRC) */ + CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + + /* Enable 32 KHz low-speed internal RC oscillator (LIRC) */ + CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk); + /* Wait for LIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); + +#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48) + /* Enable/disable 48 MHz high-speed internal RC oscillator (HIRC48) */ + if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_ENABLE) { + CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk); + /* Wait for HIRC48 clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk); + } else if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_DISABLE) { + CLK_DisableXtalRC(CLK_PWRCTL_HIRC48EN_Msk); + } +#endif + +#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), clk_pclkdiv) + /* Set CLK_PCLKDIV register on request */ + CLK->PCLKDIV = DT_PROP(DT_NODELABEL(scc), clk_pclkdiv); +#endif + +#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), core_clock) + /* Set core clock (HCLK) on request */ + CLK_SetCoreClock(DT_PROP(DT_NODELABEL(scc), core_clock)); +#endif + + /* + * Update System Core Clock + * User can use SystemCoreClockUpdate() to calculate SystemCoreClock. + */ + SystemCoreClockUpdate(); + + /* Lock protected registers */ + SYS_LockReg(); +} diff --git a/soc/nuvoton/numaker/m2l31x/soc.h b/soc/nuvoton/numaker/m2l31x/soc.h new file mode 100644 index 00000000000..5381d369676 --- /dev/null +++ b/soc/nuvoton/numaker/m2l31x/soc.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM_NUVOTON_M2L31X_SOC_H_ +#define ZEPHYR_SOC_ARM_NUVOTON_M2L31X_SOC_H_ + +/* Hardware and starter kit includes. */ +#include + +#endif /* ZEPHYR_SOC_ARM_NUVOTON_M2L31X_SOC_H_*/ diff --git a/soc/nuvoton/numaker/soc.yml b/soc/nuvoton/numaker/soc.yml index cad8f6d1fc4..ec1059c497f 100644 --- a/soc/nuvoton/numaker/soc.yml +++ b/soc/nuvoton/numaker/soc.yml @@ -4,3 +4,6 @@ family: - name: m46x socs: - name: m467 + - name: m2l31x + socs: + - name: m2l31xxx