soc: renesas: Add support for Renesas RZ/A3UL

Add support for Renesas RZ/A3UL

Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

dts/arm64/renesas/rz/rza/r9a07g063.dtsi

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <freq.h>
+#include <arm64/armv8-a.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "renesas,r9a07g063";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			clock-frequency = <DT_FREQ_M(1000)>;
+			reg = <0>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	soc {
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@11900000 {
+			compatible = "arm,gic-v3", "arm,gic";
+			reg = <0x11900000 0x10000>, /* GICD */
+				<0x11940000 0x20000>; /* GICR */
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+		};
+	};
+};

soc/renesas/rz/rza3ul/CMakeLists.txt

@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(soc.c)
+zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
+
+zephyr_include_directories(.)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/rz/rza3ul/Kconfig

@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZA3UL
+	select ARM64
+	select CPU_CORTEX_A55
+	select ARM_ARCH_TIMER
+	select HAS_RENESAS_RZ_FSP
+	select SOC_EARLY_INIT_HOOK

soc/renesas/rz/rza3ul/Kconfig.defconfig

@@ -0,0 +1,31 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RZA3UL
+
+config SYS_CLOCK_EXISTS
+	default y
+
+config NUM_IRQS
+	default 512
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 24000000
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition
+DT_CHOSEN_SRAM_ZEPHYR = zephyr,sram
+
+config BUILD_OUTPUT_ADJUST_LMA
+	default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) - \
+	$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_SRAM_ZEPHYR))"
+
+config BUILD_OUTPUT_ADJUST_LMA_SECTIONS
+	default "*;!.header"
+
+endif # SOC_SERIES_RZA3UL

soc/renesas/rz/rza3ul/Kconfig.soc

@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZA3UL
+	bool
+	select SOC_FAMILY_RENESAS_RZ
+	help
+	  Renesas RZ/A3UL series
+
+config SOC_SERIES
+	default "rza3ul" if SOC_SERIES_RZA3UL
+
+config SOC_R9A07G063U02GBG
+	bool
+	select SOC_SERIES_RZA3UL
+	help
+	  R9A07G063U02GBG
+
+config SOC
+	default "r9a07g063u02gbg" if SOC_R9A07G063U02GBG

soc/renesas/rz/rza3ul/mmu_regions.c

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm64/arm_mmu.h>
+#include <zephyr/devicetree.h>
+
+static const struct arm_mmu_region mmu_regions[] = {
+	MMU_REGION_FLAT_ENTRY("IO_REG", 0x10000000, 0x10000000,
+			      MT_DEVICE_nGnRnE | MT_RW | MT_DEFAULT_SECURE_STATE),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};

soc/renesas/rz/rza3ul/sections.ld

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_PROLOGUE(.header, CONFIG_FLASH_BASE_ADDRESS,)
+{
+	QUAD(__start)
+	QUAD(0xFFFFFFFFFFFFFFFF-__start)
+	QUAD(CONFIG_SRAM_BASE_ADDRESS)
+	QUAD(0xFFFFFFFFFFFFFFFF-CONFIG_SRAM_BASE_ADDRESS)
+	QUAD(z_mapped_size)
+	QUAD(0xFFFFFFFFFFFFFFFF-z_mapped_size)
+	FILL(0x00)
+	. += 0x1B0;
+	QUAD(0x4120505346205a52)
+	QUAD(0x69746163696c7070)
+	QUAD(0x0000000000006e6f)
+	QUAD(0x0000000000000000)
+} > FLASH
+
+z_mapped_size = z_mapped_end - z_mapped_start;

soc/renesas/rz/rza3ul/soc.c

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RZ/A3UL Group
+ */
+
+#include <zephyr/init.h>
+#include "soc.h"
+
+uint32_t SystemCoreClock;
+
+void soc_early_init_hook(void)
+{
+	/* Configure system clocks. */
+	bsp_clock_init();
+
+	/* InitFialize SystemCoreClock variable. */
+	SystemCoreClockUpdate();
+}

soc/renesas/rz/rza3ul/soc.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZA3UL_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZA3UL_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RZG3S_SOC_H_ */

soc/renesas/rz/soc.yml

@@ -1,6 +1,9 @@
 family:
   - name: renesas_rz
     series:
+      - name: rza3ul
+        socs:
+          - name: r9a07g063u02gbg
       - name: rzg3s
         socs:
           - name: r9a08g045s33gbg