diff --git a/soc/nxp/imx/imx9/CMakeLists.txt b/soc/nxp/imx/imx9/CMakeLists.txt index 369519ad7b3..7c0803be807 100644 --- a/soc/nxp/imx/imx9/CMakeLists.txt +++ b/soc/nxp/imx/imx9/CMakeLists.txt @@ -1,7 +1,9 @@ -# Copyright 2024 NXP +# Copyright 2024-2025 NXP # SPDX-License-Identifier: Apache-2.0 -if(CONFIG_SOC_MIMX9352) +if(CONFIG_SOC_MIMX9131) + add_subdirectory(imx91) +elseif(CONFIG_SOC_MIMX9352) add_subdirectory(imx93) elseif(CONFIG_SOC_MIMX9596) add_subdirectory(imx95) diff --git a/soc/nxp/imx/imx9/imx91/CMakeLists.txt b/soc/nxp/imx/imx9/imx91/CMakeLists.txt new file mode 100644 index 00000000000..4d342af6f13 --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +zephyr_compile_options(-Wno-misleading-indentation) + +zephyr_include_directories(.) + +zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imx/imx9/imx91/Kconfig b/soc/nxp/imx/imx9/imx91/Kconfig new file mode 100644 index 00000000000..a528effa490 --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/Kconfig @@ -0,0 +1,12 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX9131 + select ARM64 + select CPU_CORTEX_A55 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select HAS_MCUX if CLOCK_CONTROL + select HAS_MCUX_CCM_REV2 if CLOCK_CONTROL + select HAS_MCUX_IOMUXC if PINCTRL + select HAS_MCUX_CACHE + select KERNEL_DIRECT_MAP if HAS_MCUX diff --git a/soc/nxp/imx/imx9/imx91/Kconfig.defconfig b/soc/nxp/imx/imx9/imx91/Kconfig.defconfig new file mode 100644 index 00000000000..1f176ff4748 --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX9 + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_IMX9 diff --git a/soc/nxp/imx/imx9/imx91/Kconfig.defconfig.mimx91 b/soc/nxp/imx/imx9/imx91/Kconfig.defconfig.mimx91 new file mode 100644 index 00000000000..748117545f0 --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/Kconfig.defconfig.mimx91 @@ -0,0 +1,21 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX9131 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config NUM_IRQS + default 300 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 24000000 + +endif diff --git a/soc/nxp/imx/imx9/imx91/Kconfig.soc b/soc/nxp/imx/imx9/imx91/Kconfig.soc new file mode 100644 index 00000000000..a3a063740cd --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/Kconfig.soc @@ -0,0 +1,21 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX9131 + bool + select SOC_SERIES_IMX9 + help + NXP i.MX91 + +config SOC_PART_NUMBER_MIMX9131CVVXJ + bool + +config SOC_PART_NUMBER_MIMX9131DVVXJ + bool + +config SOC_PART_NUMBER + default "MIMX9131CVVXJ" if SOC_PART_NUMBER_MIMX9131CVVXJ + default "MIMX9131DVVXJ" if SOC_PART_NUMBER_MIMX9131DVVXJ + +config SOC + default "mimx9131" if SOC_MIMX9131 diff --git a/soc/nxp/imx/imx9/imx91/mmu_regions.c b/soc/nxp/imx/imx9/imx91/mmu_regions.c new file mode 100644 index 00000000000..62f04672b66 --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/mmu_regions.c @@ -0,0 +1,38 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +static const struct arm_mmu_region mmu_regions[] = { + MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0), + DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), + + MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1), + DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), + + MMU_REGION_FLAT_ENTRY("CCM", DT_REG_ADDR(DT_NODELABEL(ccm)), DT_REG_SIZE(DT_NODELABEL(ccm)), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), + + MMU_REGION_FLAT_ENTRY("ANA_PLL", DT_REG_ADDR(DT_NODELABEL(ana_pll)), + DT_REG_SIZE(DT_NODELABEL(ana_pll)), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), + + MMU_REGION_FLAT_ENTRY("IOMUXC", DT_REG_ADDR(DT_NODELABEL(iomuxc)), + DT_REG_SIZE(DT_NODELABEL(iomuxc)), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS), + + MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_lpuart, + (MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS)) +}; + +const struct arm_mmu_config mmu_config = { + .num_regions = ARRAY_SIZE(mmu_regions), + .mmu_regions = mmu_regions, +}; diff --git a/soc/nxp/imx/imx9/imx91/pinctrl_soc.h b/soc/nxp/imx/imx9/imx91/pinctrl_soc.h new file mode 100644 index 00000000000..da79bbfab43 --- /dev/null +++ b/soc/nxp/imx/imx9/imx91/pinctrl_soc.h @@ -0,0 +1,79 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ + +#include +#include +#include "fsl_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_HYS_SHIFT +#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT +#define MCUX_IMX_BIAS_PULL_DOWN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PD_SHIFT +#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC1_SW_PAD_CTL_PAD_PU_SHIFT +#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT +#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC1_SW_PAD_CTL_PAD_DSE_SHIFT +#define MCUX_IMX_INPUT_ENABLE_SHIFT 23 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */ +#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1) + +#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \ + ((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \ + (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \ + (DT_PROP(node_id, bias_pull_down) << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) | \ + (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \ + (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \ + ((~(0xff << DT_ENUM_IDX(node_id, drive_strength))) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \ + (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)) + +/* This struct must be present. It is used by the mcux gpio driver */ +struct pinctrl_soc_pinmux { + uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */ + uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */ + uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */ + uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */ + uint32_t input_daisy: 4; /*!< Mux value for SELECT_INPUT_DAISY register */ +}; + +struct pinctrl_soc_pin { + struct pinctrl_soc_pinmux pinmux; + uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */ +}; + +typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; + +/* This definition must be present. It is used by the mcux gpio driver */ +#define MCUX_IMX_PINMUX(node_id) \ + { \ + .mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \ + .input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \ + .mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \ + .input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \ + } + +#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ + MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx)) + +#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ + { \ + .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \ + .pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \ + }, + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \ + Z_PINCTRL_STATE_PIN_INIT)}; + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ */ diff --git a/soc/nxp/imx/soc.yml b/soc/nxp/imx/soc.yml index 64371b41c23..e955bfee6a8 100644 --- a/soc/nxp/imx/soc.yml +++ b/soc/nxp/imx/soc.yml @@ -35,6 +35,7 @@ family: - name: m4 - name: imx9 socs: + - name: mimx9131 - name: mimx9352 cpuclusters: - name: a55