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boards: nucleo_wba52cg: Update core freq to provide 48MHz on PLLQ

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PLL Q is used as 48MHz clock source, which is required for RNG

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
This commit is contained in:
Erwan Gouriou 2023-03-07 08:44:17 +01:00 • committed by Fabio Baltieri
commit e13c193acf
1 changed files with 7 additions and 3 deletions
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10
boards/arm/nucleo_wba52cg/nucleo_wba52cg.dts
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@ -70,16 +70,16 @@
&pll1 { &pll1 {
div-m = <8>; div-m = <8>;
mul-n = <100>; mul-n = <48>;
div-q = <2>; div-q = <2>;
div-r = <4>; div-r = <2>;
clocks = <&clk_hse>; clocks = <&clk_hse>;
status = "okay"; status = "okay";
}; };
&rcc { &rcc {
clocks = <&pll1>; clocks = <&pll1>;
clock-frequency = <DT_FREQ_M(100)>; clock-frequency = <DT_FREQ_M(96)>;
ahb-prescaler = <1>; ahb-prescaler = <1>;
ahb5-prescaler = <4>; ahb5-prescaler = <4>;
apb1-prescaler = <1>; apb1-prescaler = <1>;
@ -123,3 +123,7 @@
<&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
status = "okay"; status = "okay";
}; };
&rng {
status = "okay";
};