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uart/ns16550, drivers/pcie: add PCI(e) support

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A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.

The NS16550 UART driver is modified to use pcie.

pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.

This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.

Deficiencies:

64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.

The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This commit is contained in:
Charles E. Youse 2019-04-02 10:06:07 -07:00 • committed by Andrew Boie
commit e039053546
32 changed files with 968 additions and 433 deletions
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15
soc/x86/apollo_lake/Kconfig.defconfig
View file

@ -21,9 +21,6 @@ config CLFLUSH_DETECT
if UART_NS16550
config UART_NS16550_PCI
default y if PCI
config UART_NS16550_PORT_0
default y
@ -32,9 +29,6 @@ if UART_NS16550_PORT_0
config UART_NS16550_PORT_0_OPTIONS
default 0
config UART_NS16550_PORT_0_PCI
default y if PCI
endif # UART_NS16550_PORT_0
config UART_NS16550_PORT_1
@ -45,9 +39,6 @@ if UART_NS16550_PORT_1
config UART_NS16550_PORT_1_OPTIONS
default 0
config UART_NS16550_PORT_1_PCI
default y if PCI
endif # UART_NS16550_PORT_1
if UART_NS16550_PORT_2
@ -55,9 +46,6 @@ if UART_NS16550_PORT_2
config UART_NS16550_PORT_2_OPTIONS
default 0
config UART_NS16550_PORT_2_PCI
default y if PCI
endif # UART_NS16550_PORT_2
if UART_NS16550_PORT_3
@ -65,9 +53,6 @@ if UART_NS16550_PORT_3
config UART_NS16550_PORT_3_OPTIONS
default 0
config UART_NS16550_PORT_3_PCI
default y if PCI
endif # UART_NS16550_PORT_3
endif # UART_NS16550

54
soc/x86/apollo_lake/soc.h
View file

@ -45,60 +45,6 @@
*/
#define pci_pin2irq(bus, dev, pin) (pin)
/* UARTs */
#ifdef CONFIG_UART_NS16550_PCI
#ifdef CONFIG_UART_NS16550_PORT_0_PCI
#define UART_NS16550_PORT_0_PCI_CLASS 0x11
#define UART_NS16550_PORT_0_PCI_BUS 0
#define UART_NS16550_PORT_0_PCI_DEV 18
#define UART_NS16550_PORT_0_PCI_VENDOR_ID 0x8086
#define UART_NS16550_PORT_0_PCI_DEVICE_ID 0x5abc
#define UART_NS16550_PORT_0_PCI_FUNC 0
#define UART_NS16550_PORT_0_PCI_BAR 0
#endif /* CONFIG_UART_NS16550_PORT_0_PCI */
#ifdef CONFIG_UART_NS16550_PORT_1_PCI
#define UART_NS16550_PORT_1_PCI_CLASS 0x11
#define UART_NS16550_PORT_1_PCI_BUS 0
#define UART_NS16550_PORT_1_PCI_DEV 18
#define UART_NS16550_PORT_1_PCI_VENDOR_ID 0x8086
#define UART_NS16550_PORT_1_PCI_DEVICE_ID 0x5abe
#define UART_NS16550_PORT_1_PCI_FUNC 1
#define UART_NS16550_PORT_1_PCI_BAR 0
#endif /* CONFIG_UART_NS16550_PORT_1_PCI */
#ifdef CONFIG_UART_NS16550_PORT_2_PCI
#define UART_NS16550_PORT_2_PCI_CLASS 0x11
#define UART_NS16550_PORT_2_PCI_BUS 0
#define UART_NS16550_PORT_2_PCI_DEV 18
#define UART_NS16550_PORT_2_PCI_VENDOR_ID 0x8086
#define UART_NS16550_PORT_2_PCI_DEVICE_ID 0x5ac0
#define UART_NS16550_PORT_2_PCI_FUNC 2
#define UART_NS16550_PORT_2_PCI_BAR 0
#endif /* CONFIG_UART_NS16550_PORT_2_PCI */
#ifdef CONFIG_UART_NS16550_PORT_3_PCI
#define UART_NS16550_PORT_3_PCI_CLASS 0x11
#define UART_NS16550_PORT_3_PCI_BUS 0
#define UART_NS16550_PORT_3_PCI_DEV 18
#define UART_NS16550_PORT_3_PCI_VENDOR_ID 0x8086
#define UART_NS16550_PORT_3_PCI_DEVICE_ID 0x5aee
#define UART_NS16550_PORT_3_PCI_FUNC 3
#define UART_NS16550_PORT_3_PCI_BAR 0
#endif /* CONFIG_UART_NS16550_PORT_3_PCI */
#endif /* CONFIG_UART_NS16550_PCI */
/* I2C controllers */
#define I2C_DW_0_PCI_VENDOR_ID 0x8086
#define I2C_DW_0_PCI_DEVICE_ID 0x5aac