x86: implement direct interrupts
Change-Id: Icac461a361dde969f023e7aa11f0605a97a3c009 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie
parent
5a4ae76eaa
commit
e01dd87377
6 changed files with 140 additions and 15 deletions
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@ -257,7 +257,7 @@ alreadyOnIntStack:
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#endif
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/* irq_controller.h interface */
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_irq_controller_eoi
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_irq_controller_eoi_macro
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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call _int_latency_start
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@ -20,6 +20,7 @@
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#include <misc/__assert.h>
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#include <misc/printk.h>
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#include <irq.h>
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#include <logging/kernel_event_logger.h>
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extern void _SpuriousIntHandler(void *);
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extern void _SpuriousIntNoErrCodeHandler(void *);
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@ -45,3 +46,68 @@ void *__attribute__((section(".spurNoErrIsr")))
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MK_ISR_NAME(_SpuriousIntNoErrCodeHandler) =
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&_SpuriousIntNoErrCodeHandler;
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/* FIXME: IRQ direct inline functions have to be placed here and not in
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* arch/cpu.h as inline functions due to nasty circular dependency between
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* arch/cpu.h and kernel_structs.h; the inline functions typically need to
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* perform operations on _kernel. For now, leave as regular functions, a
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* future iteration will resolve this.
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* We have a similar issue with the k_event_logger functions.
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*
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* See https://jira.zephyrproject.org/browse/ZEP-1595
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*/
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#ifdef CONFIG_SYS_POWER_MANAGEMENT
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void _arch_irq_direct_pm(void)
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{
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if (_kernel.idle) {
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int32_t idle_val = _kernel.idle;
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_kernel.idle = 0;
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_sys_power_save_idle_exit(idle_val);
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}
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}
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#endif
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void _arch_isr_direct_header(void)
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{
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_int_latency_start();
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_sys_k_event_logger_interrupt();
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_sys_k_event_logger_exit_sleep();
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/* We're not going to unlock IRQs, but we still need to increment this
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* so that _is_in_isr() works
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*/
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++_kernel.nested;
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}
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void _arch_isr_direct_footer(int swap)
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{
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_irq_controller_eoi();
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_int_latency_stop();
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--_kernel.nested;
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/* Call swap if all the following is true:
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*
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* 1) swap argument was enabled to this function
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* 2) We are not in a nested interrupt
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* 3) Current thread is preemptible
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* 4) Next thread to run in the ready queue is not this thread
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*/
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if (swap && !_kernel.nested &&
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_current->base.preempt < _NON_PREEMPT_THRESHOLD &&
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_kernel.ready_q.cache != _current) {
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unsigned int flags;
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/* Fetch EFLAGS argument to _Swap() */
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__asm__ volatile (
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"pushfl\n\t"
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"popl %0\n\t"
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: "=g" (flags)
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:
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: "memory"
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);
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_Swap(flags);
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}
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}
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@ -39,6 +39,14 @@ extern "C" {
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#ifndef _ASMLANGUAGE
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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void _int_latency_start(void);
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void _int_latency_stop(void);
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#else
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#define _int_latency_start() do { } while (0)
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#define _int_latency_stop() do { } while (0)
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#endif
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/* interrupt/exception/error related definitions */
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/**
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@ -108,7 +116,8 @@ typedef struct s_isrList {
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*/
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#define NANO_CPU_INT_REGISTER(r, n, p, v, d) \
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ISR_LIST __attribute__((section(".intList"))) MK_ISR_NAME(r) = \
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static ISR_LIST __attribute__((section(".intList"))) \
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__attribute__((used)) MK_ISR_NAME(r) = \
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{&r, n, p, v, d}
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@ -194,6 +203,20 @@ typedef struct s_isrList {
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_IRQ_TO_INTERRUPT_VECTOR(irq_p); \
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})
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/** Configure a 'direct' static interrupt
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*
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* All arguments must be computable by the compiler at build time
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*
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*/
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#define _ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \
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({ \
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NANO_CPU_INT_REGISTER(isr_p, irq_p, priority_p, -1, 0); \
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_irq_controller_irq_config(_IRQ_TO_INTERRUPT_VECTOR(irq_p), (irq_p), \
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(flags_p)); \
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_IRQ_TO_INTERRUPT_VECTOR(irq_p); \
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})
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#ifdef CONFIG_X86_FIXED_IRQ_MAPPING
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/* Fixed vector-to-irq association mapping.
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* No need for the table at all.
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@ -210,6 +233,31 @@ extern unsigned char _irq_to_interrupt_vector[];
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((unsigned int) _irq_to_interrupt_vector[irq])
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#endif
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#ifdef CONFIG_SYS_POWER_MANAGEMENT
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extern void _arch_irq_direct_pm(void);
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#define _ARCH_ISR_DIRECT_PM() _arch_irq_direct_pm()
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#else
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#define _ARCH_ISR_DIRECT_PM() do { } while (0)
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#endif
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#define _ARCH_ISR_DIRECT_HEADER() _arch_isr_direct_header()
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#define _ARCH_ISR_DIRECT_FOOTER(swap) _arch_isr_direct_footer(swap)
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/* FIXME prefer these inline, but see ZEP-1595 */
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extern void _arch_isr_direct_header(void);
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extern void _arch_isr_direct_footer(int maybe_swap);
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#define _ARCH_ISR_DIRECT_DECLARE(name) \
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static inline int name##_body(void); \
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__attribute__ ((interrupt)) void name(void *stack_frame) \
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{ \
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ARG_UNUSED(stack_frame); \
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int check_reschedule; \
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ISR_DIRECT_HEADER(); \
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check_reschedule = name##_body(); \
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ISR_DIRECT_FOOTER(check_reschedule); \
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} \
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static inline int name##_body(void)
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/**
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* @brief Nanokernel Exception Stack Frame
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@ -294,14 +342,6 @@ typedef struct nanoIsf {
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#ifndef _ASMLANGUAGE
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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void _int_latency_start(void);
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void _int_latency_stop(void);
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#else
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#define _int_latency_start() do { } while (0)
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#define _int_latency_stop() do { } while (0)
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#endif
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/**
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* @brief Disable all interrupts on the CPU (inline)
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*
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@ -84,6 +84,11 @@ static inline int _irq_controller_isr_vector_get(void)
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}
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static inline void _irq_controller_eoi(void)
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{
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__irq_controller_eoi();
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}
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#else /* _ASMLANGUAGE */
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/**
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@ -98,8 +103,8 @@ static inline int _irq_controller_isr_vector_get(void)
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* saved registers eax, edx, ecx for their own purposes with impunity but
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* need to preserve all callee-saved registers.
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*/
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.macro _irq_controller_eoi
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__irq_controller_eoi
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.macro _irq_controller_eoi_macro
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__irq_controller_eoi_macro
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.endm
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#endif /* _ASMLANGUAGE */
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@ -57,9 +57,14 @@ void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
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int __irq_controller_isr_vector_get(void);
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static inline void __irq_controller_eoi(void)
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{
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*(volatile int *)(MVIC_EOI) = 0;
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}
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#else /* _ASMLANGUAGE */
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.macro __irq_controller_eoi
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.macro __irq_controller_eoi_macro
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xorl %eax, %eax /* zeroes eax */
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movl %eax, MVIC_EOI /* tell MVIC the IRQ is handled */
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.endm
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@ -27,14 +27,23 @@ void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
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int __irq_controller_isr_vector_get(void);
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static inline void __irq_controller_eoi(void)
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{
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#if CONFIG_EOI_FORWARDING_BUG
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_lakemont_eoi();
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#else
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*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI) = 0;
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#endif
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}
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#else /* _ASMLANGUAGE */
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#if CONFIG_EOI_FORWARDING_BUG
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.macro __irq_controller_eoi
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.macro __irq_controller_eoi_macro
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call _lakemont_eoi
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.endm
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#else
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.macro __irq_controller_eoi
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.macro __irq_controller_eoi_macro
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xorl %eax, %eax /* zeroes eax */
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loapic_eoi_reg = (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI)
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movl %eax, loapic_eoi_reg /* tell LOAPIC the IRQ is handled */
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