dma/cavs_hda: DMA driver for HDA on cAVS
Adds an initial driver for HDA streams on cAVS. A common code base is provided for all HDA streams while the drivers are identified differently as they have small behavior differences. Uses dma_status to describe the positions for read/write. Uses dma_reload to inform when to move the read/write positions. This closely follows how HDA is being used in SoF Simple test case is provided for both drivers. Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This commit is contained in:
Tom Burdick
Anas Nashif
parent
fda02eebf7
commit
e018a3dff7
16 changed files with 582 additions and 2 deletions
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@ -4,4 +4,4 @@ cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(intel_adsp)
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target_sources(app PRIVATE src/main.c src/smoke.c)
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target_sources(app PRIVATE src/main.c src/smoke.c src/dma.c)
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242
tests/boards/intel_adsp/hda/src/dma.c
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242
tests/boards/intel_adsp/hda/src/dma.c
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@ -0,0 +1,242 @@
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/* Copyright (c) 2022 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "arch/xtensa/cache.h"
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#include <kernel.h>
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#include <ztest.h>
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#include <cavs_ipc.h>
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#include <cavs_hda.h>
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#include <drivers/dma.h>
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#include "tests.h"
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#define IPC_TIMEOUT K_MSEC(500)
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#define DMA_BUF_SIZE 256
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#define TRANSFER_SIZE 256
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#define TRANSFER_COUNT 8
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static __aligned(128) uint8_t dma_buf[DMA_BUF_SIZE];
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static volatile int msg_cnt;
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static volatile int msg_res;
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static bool ipc_message(const struct device *dev, void *arg,
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uint32_t data, uint32_t ext_data)
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{
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printk("HDA message received, data %u, ext_data %u\n", data, ext_data);
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msg_res = data;
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msg_cnt++;
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return true;
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}
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/*
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* Tests host input streams with the DMA API
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*
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* Note that the order of operations in this test are important and things potentially will not
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* work in horrible and unexpected ways if not done as they are here.
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*/
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void test_hda_host_in_dma(void)
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{
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const struct device *dma;
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int res, channel;
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uint32_t last_msg_cnt;
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printk("smoke testing hda with fifo buffer at address %p, size %d\n",
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dma_buf, DMA_BUF_SIZE);
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cavs_ipc_set_message_handler(CAVS_HOST_DEV, ipc_message, NULL);
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printk("Using buffer of size %d at addr %p\n", DMA_BUF_SIZE, dma_buf);
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/* setup a ramp in the buffer */
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for (uint32_t i = 0; i < DMA_BUF_SIZE; i++) {
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dma_buf[i] = i & 0xff;
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}
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#if (IS_ENABLED(CONFIG_KERNEL_COHERENCE))
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zassert_true(arch_mem_coherent(dma_buf), "Buffer is unexpectedly incoherent!");
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#else
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/* The buffer is in the cached address range and must be flushed */
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zassert_false(arch_mem_coherent(dma_buf), "Buffer is unexpectedly coherent!");
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z_xtensa_cache_flush(dma_buf, DMA_BUF_SIZE);
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#endif
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dma = device_get_binding("HDA_HOST_IN");
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zassert_not_null(dma, "Expected a valid DMA device pointer");
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channel = dma_request_channel(dma, NULL);
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zassert_true(channel >= 0, "Expected a valid DMA channel");
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printk("dma channel: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel);
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hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_RESET, channel, IPC_TIMEOUT);
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printk("host reset: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel);
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hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_CONFIG,
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channel | (DMA_BUF_SIZE << 8), IPC_TIMEOUT);
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printk("host config: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel);
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struct dma_block_config block_cfg = {
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.block_size = DMA_BUF_SIZE,
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.source_address = (uint32_t)(&dma_buf[0]),
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};
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struct dma_config dma_cfg = {
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.block_count = 1,
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.channel_direction = MEMORY_TO_HOST,
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.head_block = &block_cfg,
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};
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res = dma_config(dma, channel, &dma_cfg);
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printk("dsp dma config: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel);
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zassert_ok(res, "Expected dma config to succeed");
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res = dma_start(dma, channel);
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printk("dsp dma start: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel);
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zassert_ok(res, "Expected dma start to succeed");
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hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_START, channel, IPC_TIMEOUT);
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printk("host start: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel);
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for (uint32_t i = 0; i < TRANSFER_COUNT; i++) {
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res = dma_reload(dma, channel, 0, 0, DMA_BUF_SIZE);
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zassert_ok(res, "Expected dma reload to succeed");
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printk("dsp dma reload: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel);
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struct dma_status status;
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int j;
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/* up to 10mS wait time */
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for (j = 0; j < 100; j++) {
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res = dma_get_status(dma, channel, &status);
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zassert_ok(res, "Expected dma status to succeed");
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if (status.read_position == status.write_position) {
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break;
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}
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k_busy_wait(100);
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}
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printk("dsp read write equal after %d uS: ", j*100);
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cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel);
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last_msg_cnt = msg_cnt;
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hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_VALIDATE, channel,
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IPC_TIMEOUT);
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WAIT_FOR(msg_cnt > last_msg_cnt);
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zassert_true(msg_res == 1,
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"Expected data validation to be true from Host");
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}
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hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_RESET,
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channel, IPC_TIMEOUT);
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res = dma_stop(dma, channel);
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zassert_ok(res, "Expected dma stop to succeed");
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}
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/*
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* Tests host output streams with the DMA API
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*/
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void test_hda_host_out_dma(void)
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{
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const struct device *dma;
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int res, channel;
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bool is_ramp;
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printk("smoke testing hda with fifo buffer at address %p, size %d\n",
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dma_buf, DMA_BUF_SIZE);
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cavs_ipc_set_message_handler(CAVS_HOST_DEV, ipc_message, NULL);
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printk("Using buffer of size %d at addr %p\n", DMA_BUF_SIZE, dma_buf);
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dma = device_get_binding("HDA_HOST_OUT");
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zassert_not_null(dma, "Expected a valid DMA device pointer");
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channel = dma_request_channel(dma, NULL);
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zassert_true(channel >= 0, "Expected a valid DMA channel");
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printk("dma channel: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel);
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hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_RESET,
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(channel + 7), IPC_TIMEOUT);
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printk("host reset: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel);
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hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_CONFIG,
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(channel + 7) | (DMA_BUF_SIZE << 8), IPC_TIMEOUT);
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printk("host config: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel);
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struct dma_block_config block_cfg = {
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.block_size = DMA_BUF_SIZE,
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.source_address = (uint32_t)(&dma_buf[0]),
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};
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struct dma_config dma_cfg = {
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.block_count = 1,
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.channel_direction = HOST_TO_MEMORY,
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.head_block = &block_cfg,
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};
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res = dma_config(dma, channel, &dma_cfg);
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printk("dsp dma config: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel);
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zassert_ok(res, "Expected dma config to succeed");
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res = dma_start(dma, channel);
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printk("dsp dma start: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel);
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zassert_ok(res, "Expected dma start to succeed");
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hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_START, (channel + 7), IPC_TIMEOUT);
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printk("host start: ");
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cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel);
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for (uint32_t i = 0; i < TRANSFER_COUNT; i++) {
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hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_SEND,
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(channel + 7) | (DMA_BUF_SIZE << 8), IPC_TIMEOUT);
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printk("host send: ");
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cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel);
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/* TODO add a dma_poll() style call for xfer ready/complete maybe? */
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WAIT_FOR(cavs_hda_buf_full(HDA_HOST_OUT_BASE, channel));
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printk("dsp wait for full: ");
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cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel);
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#if (IS_ENABLED(CONFIG_KERNEL_COHERENCE))
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zassert_true(arch_mem_coherent(dma_buf), "Buffer is unexpectedly incoherent!");
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#else
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/* The buffer is in the cached address range and must be invalidated
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* prior to reading.
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*/
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zassert_false(arch_mem_coherent(dma_buf), "Buffer is unexpectedly coherent!");
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z_xtensa_cache_inv(dma_buf, DMA_BUF_SIZE);
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#endif
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is_ramp = true;
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for (int j = 0; j < DMA_BUF_SIZE; j++) {
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printk("dma_buf[%d] = %d\n", j, dma_buf[j]);
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if (dma_buf[j] != j) {
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is_ramp = false;
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}
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}
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zassert_true(is_ramp, "Expected data to be a ramp");
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res = dma_reload(dma, channel, 0, 0, DMA_BUF_SIZE);
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zassert_ok(res, "Expected dma reload to succeed");
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printk("dsp dma reload: "); cavs_hda_dbg("host_out", HDA_HOST_IN_BASE, channel);
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}
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hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_RESET, (channel + 7), IPC_TIMEOUT);
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printk("host reset: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel);
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res = dma_stop(dma, channel);
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zassert_ok(res, "Expected dma stop to succeed");
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printk("dsp dma stop: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel);
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}
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@ -10,7 +10,8 @@ void test_main(void)
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{
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ztest_test_suite(intel_adsp_hda,
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ztest_unit_test(test_hda_host_in_smoke),
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ztest_unit_test(test_hda_host_out_smoke)
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ztest_unit_test(test_hda_host_out_smoke),
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ztest_unit_test(test_hda_host_in_dma)
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);
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ztest_run_test_suite(intel_adsp_hda);
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@ -13,6 +13,7 @@
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void test_hda_host_in_smoke(void);
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void test_hda_host_out_smoke(void);
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void test_hda_host_in_dma(void);
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static inline void hda_ipc_msg(const struct device *dev, uint32_t data,
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uint32_t ext, k_timeout_t timeout)
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