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riscv: implement CONFIG_IRQ_OFFLOAD_NESTED

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It can easily be done now, so why not. Suffice to increment the nested
count like with actual IRQs.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2022-03-14 14:51:04 -04:00 • committed by Anas Nashif
commit df852a0b77
2 changed files with 10 additions and 7 deletions
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1
arch/Kconfig
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@ -108,6 +108,7 @@ config RISCV
select HAS_DTS
select ARCH_SUPPORTS_COREDUMP
select ARCH_HAS_THREAD_LOCAL_STORAGE
select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
select SCHED_IPI_SUPPORTED if SMP
imply XIP
help

16
arch/riscv/core/isr.S
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@ -326,19 +326,21 @@ do_irq_offload:
lr a1, __z_arch_esf_t_a0_OFFSET(sp)
lr a0, __z_arch_esf_t_a1_OFFSET(sp)
/* Set _kernel.cpus[0].nested variable to 1 */
la t1, _kernel
li t0, 1
sw t0, _kernel_offset_to_nested(t1)
/* Increment _kernel.cpus[0].nested variable */
la t2, _kernel
lw t3, _kernel_offset_to_nested(t2)
addi t4, t3, 1
sw t4, _kernel_offset_to_nested(t2)
bnez t3, 1f
/* Switch to interrupt stack */
mv t0, sp
lr sp, _kernel_offset_to_irq_stack(t1)
lr sp, _kernel_offset_to_irq_stack(t2)
/* Save original sp on the interrupt stack */
/* Save thread stack pointer on interrupt stack */
addi sp, sp, -16
sr t0, 0(sp)
1:
/* Execute provided routine (argument is in a0 already). */
jalr ra, a1, 0