soc: boards: Add MediaTek MT8195 Audio DSP

This is a soc/board integration for the MediaTek Audio DSP device on
the MT8195 SOC, along with a Zephyr mtk_adsp soc integration that will
work to support similar 8186 and 8188 device shortly.

A python loader (similar to cavsload.py) is included that will run in
developer mode on current chromebooks (an HP x360 13b-ca000 was
tested) with an unmodified kernel.

Signed-off-by: Andy Ross <andyross@google.com>

boards/mediatek/mt8195_adsp/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# Copyright 2023 The ChromiumOS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MT8195_ADSP
+
+config BOARD
+	default "mt8195_adsp"
+
+endif # BOARD_MT8195_ADSP

boards/mediatek/mt8195_adsp/Kconfig.mt8195_adsp

@@ -0,0 +1,5 @@
+# Copyright 2023 The ChromiumOS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MT8195_ADSP
+	bool "Mediatek MT8195 Audio DSP"

boards/mediatek/mt8195_adsp/board.yml

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+boards:
+  - name: mt8195_adsp
+    vendor: mediatek
+    socs:
+      - name: mt8195_adsp

boards/mediatek/mt8195_adsp/mt8195_adsp.dts

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+/* Copyright 2023 The ChromiumOS Authors
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+
+/dts-v1/;
+/ {
+
+#address-cells = <1>;
+#size-cells = <1>;
+
+sram0: memory@40000000 {
+	 device_type = "memory";
+	 compatible = "mmio-sram";
+	 reg = <0x40000000 DT_SIZE_K(256)>;
+};
+
+dram0: memory@60000000 {
+	device_type = "memory";
+	compatible = "mmio-sram";
+	reg = <0x60000000 DT_SIZE_M(17)>;
+};
+
+soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpuclk: cpuclk@10000000 {
+		compatible = "mediatek,mt8195_cpuclk";
+		reg = <0x10000000 380>;
+		cg_reg = <0x10720180>;
+		pll_ctrl_reg = <0x1000c7e0>;
+		freqs_mhz = <26 370 540 720>;
+	};
+
+	core_intc: core_intc@0 {
+		compatible = "cdns,xtensa-core-intc";
+		reg = <0 4>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
+	intc1: intc@10680130 {
+		compatible = "mediatek,adsp_intc";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0x10680130 4>;
+		status-reg = <0x10680150>;
+		interrupts = <1 0 0>;
+		mask = <0x3ffffff0>;
+		interrupt-parent = <&core_intc>;
+	};
+
+	intc23: intc@108030f4 {
+		compatible = "mediatek,adsp_intc";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0x108030f4 4>;
+		status-reg = <0x108030fc>;
+		interrupts = <23 0 0>;
+		mask = <0xffff>;
+		interrupt-parent = <&core_intc>;
+	};
+
+	ostimer64: ostimer64@1080d080 {
+		compatible = "mediatek,ostimer64";
+		reg = <0x1080d080 28>;
+	};
+
+	ostimer0: ostimer@1080d000 {
+		compatible = "mediatek,ostimer";
+		reg = <0x1080d000 16>;
+		interrupt-parent = <&intc23>;
+		interrupts = <11 0 0>;
+	};
+
+	mbox0: mbox@10816000 {
+		compatible = "mediatek,mbox";
+		reg = <0x10816000 56>;
+		interrupt-parent = <&intc23>;
+		interrupts = <0 0 0>;
+	};
+
+	mbox1: mbox@10817000 {
+		compatible = "mediatek,mbox";
+		reg = <0x10817000 56>;
+		interrupt-parent = <&intc23>;
+		interrupts = <1 0 0>;
+	};
+}; /* soc */
+
+chosen { };
+aliases { };
+
+};

boards/mediatek/mt8195_adsp/mt8195_adsp_defconfig

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+# Copyright 2023 The ChromiumOS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_MT8195_ADSP=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=13000000