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boards: arm: efr32bg27_brd2602: Initial support

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Adds initial support for efr32bg27_brd2602 - Thunderboard-style board.
Supported features are:
* counter
* gpio
* uart

Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
This commit is contained in:
Krzysztof Boronski 2023-03-16 15:25:21 +01:00 • committed by Carles Cufí
commit df7f10422e
14 changed files with 262 additions and 2 deletions
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5
boards/arm/efr32_thunderboard/Kconfig.board
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@ -7,3 +7,8 @@ config BOARD_EFR32BG_SLTB010A
bool "SiLabs EFR32BG-SLTB010A (Thunderboard EFR32BG22)"
depends on SOC_SERIES_EFR32BG22
select SOC_PART_NUMBER_EFR32BG22C224F512IM40
config BOARD_EFR32BG27_BRD2602A
bool "SiLabs EFR32BG27C140F768IM40 (EFR32BG27 +8 dBm Dev Kit Board)"
depends on SOC_SERIES_EFR32BG27
select SOC_PART_NUMBER_EFR32BG27C140F768IM40

10
boards/arm/efr32_thunderboard/Kconfig.defconfig
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@ -10,11 +10,19 @@ config BOARD
endif # BOARD_EFR32BG_SLTB010A
if BOARD_EFR32BG27_BRD2602A
config BOARD
default "efr32bg27_brd2602a"
endif # BOARD_EFR32BG27_BRD2602A
config CMU_HFXO_FREQ
default 40000000
config CMU_LFXO_FREQ
default 32768
<<<<<<< HEAD
if BT
@ -34,3 +42,5 @@ endchoice
endif # BT
endif # BOARD_EFR32BG_SLTB010A
=======
>>>>>>> 4a57ca65b7 (boards: arm: efr32bg27_brd2602: Initial support)

81
boards/arm/efr32_thunderboard/efr32bg27_brd2602a.dts Normal file
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@ -0,0 +1,81 @@
/*
* Copyright (c) 2023 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
/* TODO: Adapt GPIO to BG27 instead of using BG22 DTSi */
#include <silabs/efr32bg27.dtsi>
#include <silabs/efr32bg22-pinctrl.dtsi>
#include "thunderboard.dtsi"
/ {
model = "Silicon Labs EFR32BG27C140F768IM40 Thunderboard-style board";
compatible = "silabs,efr32bg27c140f768im40", "silabs,efr32bg27";
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led0;
sw0 = &button0;
i2c-pin = &i2c_pin;
spi-flash0 = &mx25r80;
spi0 = &usart0;
watchdog0 = &wdog0;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_HIGH>;
label = "LED 0";
};
};
};
&flash0 {
partitions {
/* Reserve 32 kB for the bootloader */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x0 0x00008000>;
read-only;
};
/* Reserve 320 kB for the application in slot 0 */
slot0_partition: partition@8000 {
label = "image-0";
reg = <0x00008000 0x00050000>;
};
/* Reserve 320 kB for the application in slot 1 */
slot1_partition: partition@58000 {
label = "image-1";
reg = <0x00058000 0x00050000>;
};
/* Reserve 32 kB for the scratch partition */
scratch_partition: partition@a8000 {
label = "image-scratch";
reg = <0x000a8000 0x00008000>;
};
/* Set 64Kb of storage at the end of the 768KB of flash */
storage_partition: partition@b0000 {
label = "storage";
reg = <0x000b0000 0x00010000>;
};
};
};
&usart0 {
interrupts = <16 0>, <17 0>;
interrupt-names = "rx", "tx";
};
&usart1 {
interrupts = <18 0>, <19 0>;
interrupt-names = "rx", "tx";
};

18
boards/arm/efr32_thunderboard/efr32bg27_brd2602a.yaml Normal file
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@ -0,0 +1,18 @@
identifier: efr32bg27_brd2602a
name: EFR32BG27_BRD2602A
type: mcu
arch: arm
ram: 64
flash: 768
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- counter
- gpio
- uart
testing:
ignore_tags:
- net
- bluetooth

17
boards/arm/efr32_thunderboard/efr32bg27_brd2602a_defconfig Normal file
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@ -0,0 +1,17 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM_MPU=y
CONFIG_SOC_SERIES_EFR32BG27=y
CONFIG_BOARD_EFR32BG27_BRD2602A=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=76800000
CONFIG_CMU_HFCLK_HFXO=y
CONFIG_SOC_GECKO_EMU_DCDC=y
CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_CMU_HFCLK_HFRCO=y
CONFIG_PINCTRL=y

3
drivers/gpio/gpio_gecko.c
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@ -26,12 +26,13 @@
#define GET_GECKO_GPIO_INDEX(id) DT_INST_PROP(id, peripheral_id)
#else
#if defined(CONFIG_SOC_SERIES_EFR32BG22) || \
defined(CONFIG_SOC_SERIES_EFR32BG27) || \
defined(CONFIG_SOC_SERIES_EFR32MG21) || \
defined(CONFIG_SOC_SERIES_EFR32MG24)
#define GECKO_GPIO_PORT_ADDR_SPACE_SIZE sizeof(GPIO_PORT_TypeDef)
#else
#define GECKO_GPIO_PORT_ADDR_SPACE_SIZE sizeof(GPIO_P_TypeDef)
#endif /* defined(CONFIG_SOC_SERIES_EFM32HG) || defined(CONFIG_SOC_SERIES_EFM32WG) */
#endif
/* Assumption for calculating gpio index:
* 1. Address space of the first GPIO port is the address space for GPIO port A
*/

42
dts/arm/silabs/efr32bg27.dtsi Normal file
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@ -0,0 +1,42 @@
/*
* Copyright (c) 2023 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "efr32bg2x.dtsi"
#include <mem.h>
/ {
soc {
stimer0: stimer@50048000 {
compatible = "silabs,gecko-stimer";
reg = <0x50048000 0x3054>;
interrupts = <12 0>;
clock-frequency = <32768>;
prescaler = <1>;
status = "disabled";
};
};
};
&sram0 {
reg = <0x20000000 DT_SIZE_K(64)>;
};
&flash0 {
reg = <0x08000000 DT_SIZE_K(768)>;
};
&gpio {
interrupts = <30 2 31 2>;
};
&i2c0 {
interrupts = <32 0>;
};
&i2c1 {
interrupts = <33 0>;
};

10
soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.efr32bg27 Normal file
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@ -0,0 +1,10 @@
# Silicon Labs EFR32BG27 (Blue Gecko) MCU configuration options
# Copyright (c) 2023 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config GPIO_GECKO
default y
config SOC_FLASH_GECKO
default n

23
soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.series Normal file
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@ -0,0 +1,23 @@
# Silicon Labs EFR32BG27 (Blue Gecko) MCU configuration options
# Copyright (c) 2023 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_EFR32BG27
config SOC_SERIES
default "efr32bg27"
config SOC_PART_NUMBER
default "EFR32BG27C140F768IM40" if SOC_PART_NUMBER_EFR32BG27C140F768IM40
config NUM_IRQS
# must be >= the highest interrupt number used
default 66
config PM
select COUNTER
source "soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.efr32bg27"
endif # SOC_SERIES_EFR32BG27

22
soc/arm/silabs_exx32/efr32bg27/Kconfig.series Normal file
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@ -0,0 +1,22 @@
# Silicon Labs EFR32BG27 (Blue Gecko) MCU
# Copyright (c) Antmicro 2023 <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_EFR32BG27
bool "EFR32BG27 Series MCU"
select ARM
select ARMV8_M_DSP
select ARM_TRUSTZONE_M
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select CPU_HAS_ARM_SAU
select CPU_HAS_FPU
select HAS_SILABS_GECKO
select HAS_SWO
select SOC_FAMILY_EXX32
select SOC_GECKO_CMU
select SOC_GECKO_CORE
select SOC_GECKO_DEV_INIT
help
Enable support for EFR32BG27 Blue Gecko MCU series

8
soc/arm/silabs_exx32/efr32bg27/Kconfig.soc Normal file
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@ -0,0 +1,8 @@
# Silicon Labs EFR32BG27 (Blue Gecko) MCU series
# Copyright (c) 2023 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_PART_NUMBER_EFR32BG27C140F768IM40
bool
depends on SOC_SERIES_EFR32BG27

5
soc/arm/silabs_exx32/efr32bg27/linker.ld Normal file
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@ -0,0 +1,5 @@
/*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

18
soc/arm/silabs_exx32/efr32bg27/soc.h Normal file
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@ -0,0 +1,18 @@
/* Copyright (c) 2023 Antmicro <www.antmicro.com>
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Register access macros for the EFR32BG27 SoC
*/
#ifndef EFR32BG27_SOC_H_
#define EFR32BG27_SOC_H_
#ifndef _ASMLANGUAGE
#include <em_common.h>
#include "../common/soc_gpio.h"
#endif /* _ASMLANGUAGE */
#endif /* EFR32BG27_SOC_H_ */

2
west.yml
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@ -126,7 +126,7 @@ manifest:
groups:
- hal
- name: hal_silabs
revision: 793db3cb744a6873f5564a901d6c9a1bb7dd5fd8
revision: 229c1cdfcdba834c8db0978cf83235ba69b63ec0
path: modules/hal/silabs
groups:
- hal