drivers/timer: it8xxx2 platform driver/timer
This commit is about the it8xxx2 timer driver. We use the timer 5 as system timer for count time, so the timer interrupt is trigged by it. Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
This commit is contained in:
Cheryl Su
Anas Nashif
parent
362eb1cdff
commit
df6125f70d
3 changed files with 254 additions and 0 deletions
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@ -7,6 +7,7 @@ zephyr_sources_ifdef(CONFIG_ARM_ARCH_TIMER arm_arch_timer.c)
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zephyr_sources_ifdef(CONFIG_LOAPIC_TIMER loapic_timer.c)
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zephyr_sources_ifdef(CONFIG_APIC_TIMER apic_timer.c)
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zephyr_sources_ifdef(CONFIG_ALTERA_AVALON_TIMER altera_avalon_timer_hal.c)
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zephyr_sources_ifdef(CONFIG_ITE_IT8XXX2_TIMER ite_it8xxx2_timer.c)
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zephyr_sources_ifdef(CONFIG_NRF_RTC_TIMER nrf_rtc_timer.c)
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zephyr_sources_ifdef(CONFIG_STM32_LPTIM_TIMER stm32_lptim_timer.c)
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zephyr_sources_ifdef(CONFIG_RISCV_MACHINE_TIMER riscv_machine_timer.c)
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@ -145,6 +145,13 @@ config ALTERA_AVALON_TIMER
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with Nios II and possibly other Altera soft CPUs. It provides the
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standard "system clock driver" interfaces.
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config ITE_IT8XXX2_TIMER
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bool "ITE it8xxx2 timer driver"
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depends on SOC_IT8XXX2
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help
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This module implements a kernel device driver for the ITE it8xxx2
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HW timer model
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config NRF_RTC_TIMER
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bool "nRF Real Time Counter (NRF_RTC1) Timer"
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depends on CLOCK_CONTROL
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246
drivers/timer/ite_it8xxx2_timer.c
Normal file
246
drivers/timer/ite_it8xxx2_timer.c
Normal file
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@ -0,0 +1,246 @@
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/*
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* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr.h>
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#include <sys/util.h>
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#include <drivers/timer/system_timer.h>
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#include <soc.h>
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#include <sys/printk.h>
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/**
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* Macro Define
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*/
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#define EXT_TIMER_BASE (DT_REG_ADDR_BY_IDX(DT_NODELABEL(timer), 0))
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#define EXT_CTL_B (EXT_TIMER_BASE + 0x10)
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#define EXT_PSC_B (EXT_TIMER_BASE + 0x11)
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#define EXT_LLR_B (EXT_TIMER_BASE + 0x14)
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#define EXT_LHR_B (EXT_TIMER_BASE + 0x15)
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#define EXT_LH2R_B (EXT_TIMER_BASE + 0x16)
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#define EXT_LH3R_B (EXT_TIMER_BASE + 0x17)
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#define EXT_CNTO_B (EXT_TIMER_BASE + 0x48)
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#define CTIMER_HW_TIMER_INDEX EXT_TIMER_3
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#define ETIMER_HW_TIMER_INDEX EXT_TIMER_5
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#define RTIMER_HW_TIMER_INDEX EXT_TIMER_7
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#define CYC_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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#define MAX_TICKS ((0x00ffffffu - CYC_PER_TICK) / CYC_PER_TICK)
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#define MAX_TIMER_NUM 8
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#define REG_ADDR_OFFSET(idx) (idx * MAX_TIMER_NUM)
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#define IDX_SHIFT(idx, rsh, lsh) ((idx >> rsh) << lsh)
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enum _EXT_TIMER_PRESCALE_TYPE_ {
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ET_PSR_32K,
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ET_PSR_1K,
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ET_PSR_32,
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ET_PSR_8M,
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};
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enum _EXT_TIMER_IDX_ {
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EXT_TIMER_3 = 0, /* ctimer */
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EXT_TIMER_4, /* ctimer */
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EXT_TIMER_5, /* etimer */
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EXT_TIMER_6, /* NULL */
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EXT_TIMER_7, /* rtimer */
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EXT_TIMER_8 /* NULL */
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};
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/* Be careful of overflow issue */
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#define MILLI_SEC_TO_COUNT(hz, ms) ((hz) * (ms) / 1000)
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#define MICRO_SEC_TO_COUNT(hz, us) ((hz) * (us) / 1000000)
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/**
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* ITE timer control api
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*/
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static void ite_timer_reload(uint8_t idx, uint32_t cnt)
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{
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/* timer_start */
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sys_set_bit((EXT_CTL_B + REG_ADDR_OFFSET(idx)), 0);
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sys_write8(((cnt >> 24) & 0xFF), (EXT_LH3R_B + REG_ADDR_OFFSET(idx)));
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sys_write8(((cnt >> 16) & 0xFF), (EXT_LH2R_B + REG_ADDR_OFFSET(idx)));
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sys_write8(((cnt >> 8) & 0xFF), (EXT_LHR_B + REG_ADDR_OFFSET(idx)));
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sys_write8(((cnt >> 0) & 0xFF), (EXT_LLR_B + REG_ADDR_OFFSET(idx)));
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}
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/* The following function:
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* disable, enable, check_flag, clear_flag, wait,
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* can be used only for Timer #3 ~ #7
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*/
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static void ite_timer_disable(uint8_t idx)
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{
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CLEAR_MASK(IER19, (BIT(3 + (idx))));
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}
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static void ite_timer_enable(uint8_t idx)
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{
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SET_MASK(IER19, (BIT(3 + (idx))));
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}
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static void ite_timer_clear_flag(uint8_t idx)
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{
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ISR19 = BIT(3 + (idx));
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}
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/**
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* timer_init()
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*/
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static int timer_init(uint8_t idx, uint8_t psr, uint8_t initial_state,
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uint8_t enable_isr, uint32_t cnt)
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{
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/* Setup Triggered Mode -> Rising-Edge Trig. */
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if (idx != EXT_TIMER_8) {
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IELMR19 |= BIT(3 + idx);
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IPOLR19 &= (~(BIT(3 + idx)));
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} else {
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IELMR10 |= BIT(0);
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IPOLR10 &= (~(BIT(0)));
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}
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/* Setup prescaler */
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sys_write8(psr, (EXT_PSC_B + REG_ADDR_OFFSET(idx)));
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/* Reload counter */
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ite_timer_reload(idx, cnt);
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/* Start counting or not */
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if (initial_state) {
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/* timer restart */
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/* timer_stop */
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sys_clear_bit((EXT_CTL_B + REG_ADDR_OFFSET(idx)), 0);
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/* timer_start */
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sys_set_bit((EXT_CTL_B + REG_ADDR_OFFSET(idx)), 0);
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} else {
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/* timer_stop */
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sys_clear_bit((EXT_CTL_B + REG_ADDR_OFFSET(idx)), 0);
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}
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/* Enable ISR or not & Clear flag */
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if (idx != EXT_TIMER_8) {
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if (enable_isr) {
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ite_timer_enable(idx);
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} else {
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ite_timer_disable(idx);
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}
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ite_timer_clear_flag(idx);
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} else {
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if (enable_isr) {
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SET_MASK(IER10, BIT(0));
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} else {
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CLEAR_MASK(IER10, BIT(0));
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}
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ISR10 = BIT(0);
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}
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return 0;
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}
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static int timer_init_ms(uint8_t idx, uint8_t psr, uint8_t initial_state,
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uint8_t enable_isr, uint32_t u32MilliSec)
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{
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uint32_t cnt;
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if (psr == ET_PSR_32K) {
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cnt = MILLI_SEC_TO_COUNT(32768, u32MilliSec);
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} else if (psr == ET_PSR_1K) {
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cnt = MILLI_SEC_TO_COUNT(1024, u32MilliSec);
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} else if (psr == ET_PSR_32) {
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cnt = MILLI_SEC_TO_COUNT(32, u32MilliSec);
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} else if (psr == ET_PSR_8M) {
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cnt = u32MilliSec * 8000; /* fixed overflow issue */
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} else {
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return -1;
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}
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/* 24-bits only */
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if (cnt >> 24) {
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return -2;
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}
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return timer_init(idx, psr, initial_state, enable_isr, cnt);
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}
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static void timer_init_combine(uint8_t idx, uint8_t bEnable)
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{
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if (bEnable) {
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sys_set_bit((EXT_CTL_B + IDX_SHIFT(idx, 1, (1 + 3))), 3);
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} else {
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sys_clear_bit((EXT_CTL_B + IDX_SHIFT(idx, 1, (1 + 3))), 3);
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}
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}
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static uint32_t get_timer_combine_count(uint8_t idx)
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{
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return sys_read32(EXT_CNTO_B + ((IDX_SHIFT(idx, 1, 1) + 1) * 4));
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}
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static void timer_count_reset(uint8_t idx, uint32_t cnt)
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{
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/* Reload counter */
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ite_timer_reload(idx, cnt);
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/* Start counting or not */
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/* timer_stop */
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sys_clear_bit((EXT_CTL_B + REG_ADDR_OFFSET(idx)), 0);
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/* timer_start */
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sys_set_bit((EXT_CTL_B + REG_ADDR_OFFSET(idx)), 0);
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}
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static struct k_spinlock lock;
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static volatile uint32_t accumulated_cycle_count;
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static void timer_isr(const void *unused)
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{
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ARG_UNUSED(unused);
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k_spinlock_key_t key = k_spin_lock(&lock);
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/* timer_stop */
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sys_clear_bit((EXT_CTL_B + ((ETIMER_HW_TIMER_INDEX) * MAX_TIMER_NUM)),
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0);
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uint32_t dticks = (get_timer_combine_count(CTIMER_HW_TIMER_INDEX)
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- accumulated_cycle_count) / CYC_PER_TICK;
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accumulated_cycle_count += dticks * CYC_PER_TICK;
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k_spin_unlock(&lock, key);
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z_clock_announce(dticks);
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}
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int z_clock_driver_init(const struct device *device)
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{
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timer_init_combine(CTIMER_HW_TIMER_INDEX, TRUE);
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timer_init(CTIMER_HW_TIMER_INDEX, ET_PSR_32K, TRUE, FALSE, 0);
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irq_connect_dynamic(DT_IRQ_BY_IDX(DT_NODELABEL(timer), 5, irq),
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0, timer_isr, NULL,
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DT_IRQ_BY_IDX(DT_NODELABEL(timer), 5, flags));
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timer_init_ms(ETIMER_HW_TIMER_INDEX, ET_PSR_32K, FALSE, TRUE, 0);
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return 0;
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}
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void z_clock_set_timeout(int32_t ticks, bool idle)
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{
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ARG_UNUSED(idle);
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k_spinlock_key_t key = k_spin_lock(&lock);
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ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
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ticks = MAX(MIN(ticks, (int32_t)MAX_TICKS), 1);
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timer_count_reset(ETIMER_HW_TIMER_INDEX, ticks * CYC_PER_TICK);
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k_spin_unlock(&lock, key);
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}
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uint32_t z_clock_elapsed(void)
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{
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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return 0;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint32_t ret = (get_timer_combine_count(CTIMER_HW_TIMER_INDEX)
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- accumulated_cycle_count) / CYC_PER_TICK;
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k_spin_unlock(&lock, key);
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return ret;
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}
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uint32_t z_timer_cycle_get_32(void)
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{
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return get_timer_combine_count(CTIMER_HW_TIMER_INDEX);
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}
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