michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: intc: ioapic: convert to DT_INST defines

Browse source 
Convert driver to use DT_INST_ defines.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-02-18 08:05:16 -06:00 • committed by Kumar Gala
commit df45e4df77
7 changed files with 8 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

10
drivers/interrupt_controller/intc_ioapic.c
View file

@ -62,6 +62,7 @@
#include <drivers/interrupt_controller/loapic.h> /* public API declarations and registers */
#include "intc_ioapic_priv.h"
#define IOAPIC_REG DT_INST_0_INTEL_IOAPIC_BASE_ADDRESS
#define BITS_PER_IRQ 3
#define IOAPIC_BITFIELD_HI_LO 0
#define IOAPIC_BITFIELD_LVL_EDGE 1
@ -333,9 +334,8 @@ static u32_t __IoApicGet(s32_t offset)
key = irq_lock();
*((volatile u32_t *)
(DT_IOAPIC_BASE_ADDRESS + IOAPIC_IND)) = (char)offset;
value = *((volatile u32_t *)(DT_IOAPIC_BASE_ADDRESS + IOAPIC_DATA));
*((volatile u32_t *) (IOAPIC_REG + IOAPIC_IND)) = (char)offset;
value = *((volatile u32_t *)(IOAPIC_REG + IOAPIC_DATA));
irq_unlock(key);
@ -360,8 +360,8 @@ static void __IoApicSet(s32_t offset, u32_t value)
key = irq_lock();
*(volatile u32_t *)(DT_IOAPIC_BASE_ADDRESS + IOAPIC_IND) = (char)offset;
*((volatile u32_t *)(DT_IOAPIC_BASE_ADDRESS + IOAPIC_DATA)) = value;
*(volatile u32_t *)(IOAPIC_REG + IOAPIC_IND) = (char)offset;
*((volatile u32_t *)(IOAPIC_REG + IOAPIC_DATA)) = value;
irq_unlock(key);
}

2
soc/x86/apollo_lake/dts_fixup.h
View file

@ -11,8 +11,6 @@
#define DT_RAM_SIZE CONFIG_SRAM_SIZE
#define DT_ROM_SIZE CONFIG_FLASH_SIZE
#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_INST_0_NS16550_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_SIZE DT_INST_0_NS16550_SIZE
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_INST_0_NS16550_CURRENT_SPEED

2
soc/x86/apollo_lake/soc.c
View file

@ -24,7 +24,7 @@
MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4 * 1024, MMU_ENTRY_WRITE);
/* ioapic */
MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, 1024 * 1024, MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_INST_0_INTEL_IOAPIC_BASE_ADDRESS, 1024 * 1024, MMU_ENTRY_WRITE);
#ifdef CONFIG_HPET_TIMER
MMU_BOOT_REGION(DT_INST_0_INTEL_HPET_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);

2
soc/x86/atom/dts_fixup.h
View file

@ -26,6 +26,4 @@
#define DT_ROM_SIZE CONFIG_FLASH_SIZE
#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
/* End of SoC Level DTS fixup file */

2
soc/x86/atom/soc.c
View file

@ -23,7 +23,7 @@
MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4*1024, MMU_ENTRY_WRITE);
/*ioapic */
MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, 1024*1024, MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_INST_0_INTEL_IOAPIC_BASE_ADDRESS, 1024*1024, MMU_ENTRY_WRITE);
/* peripherals */
MMU_BOOT_REGION(0xB0000000, 128*1024, MMU_ENTRY_WRITE);

3
soc/x86/ia32/dts_fixup.h
View file

@ -26,7 +26,4 @@
#define DT_ROM_SIZE CONFIG_FLASH_SIZE
#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
/* End of SoC Level DTS fixup file */

2
soc/x86/ia32/soc.c
View file

@ -22,7 +22,7 @@
#ifdef CONFIG_X86_MMU
MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, MB(1), MMU_ENTRY_WRITE);
MMU_BOOT_REGION(DT_INST_0_INTEL_IOAPIC_BASE_ADDRESS, MB(1), MMU_ENTRY_WRITE);
#ifdef CONFIG_HPET_TIMER
MMU_BOOT_REGION(DT_INST_0_INTEL_HPET_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);