From dea2e642b236a08a3cb99088d3b3f826299780cc Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Mon, 25 Apr 2022 16:57:37 -0500 Subject: [PATCH] soc: mimx8ml8_m7: add pin control support for mimx8ml8_m7 Add pin control support for IOMUXC peripheral present on mimx8ml8_m7 soc. This reuses the existing pin control driver for the IOMUXC peripheral, but uses a new header and compatible binding to handle the different register layout on this SOC. Signed-off-by: Daniel DeGrasse --- dts/arm/nxp/nxp_imx8ml_m7.dtsi | 175 ++++++++++++++++++ dts/bindings/pinctrl/nxp,imx8mp-pinctrl.yaml | 94 ++++++++++ .../mimx8ml8_m7/Kconfig.defconfig.series | 4 + soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.soc | 1 + soc/arm/nxp_imx/mimx8ml8_m7/pinctrl_soc.h | 83 +++++++++ 5 files changed, 357 insertions(+) create mode 100644 dts/bindings/pinctrl/nxp,imx8mp-pinctrl.yaml create mode 100644 soc/arm/nxp_imx/mimx8ml8_m7/pinctrl_soc.h diff --git a/dts/arm/nxp/nxp_imx8ml_m7.dtsi b/dts/arm/nxp/nxp_imx8ml_m7.dtsi index f0a189570b0..9a3dfc3f61d 100644 --- a/dts/arm/nxp/nxp_imx8ml_m7.dtsi +++ b/dts/arm/nxp/nxp_imx8ml_m7.dtsi @@ -87,6 +87,16 @@ #clock-cells = <3>; }; + iomuxc: iomuxc@30330000 { + compatible = "nxp,imx-iomuxc"; + reg = <0x30330000 DT_SIZE_K(64)>; + status = "okay"; + pinctrl: pinctrl { + status = "okay"; + compatible = "nxp,imx8mp-pinctrl"; + }; + }; + gpio1: gpio@30200000 { compatible = "nxp,imx-gpio"; reg = <0x30200000 DT_SIZE_K(64)>; @@ -188,3 +198,168 @@ &nvic { arm,num-irq-priority-bits = <4>; }; + + +/* + * GPIO pinmux options. These options define the pinmux settings + * for GPIO ports on the package, so that the GPIO driver can + * select GPIO mux options during GPIO configuration. + */ + +&gpio1{ + pinmux = <&iomuxc_gpio1_io00_gpio_io_gpio1_io0>, + <&iomuxc_gpio1_io01_gpio_io_gpio1_io1>, + <&iomuxc_gpio1_io02_gpio_io_gpio1_io2>, + <&iomuxc_gpio1_io03_gpio_io_gpio1_io3>, + <&iomuxc_gpio1_io04_gpio_io_gpio1_io4>, + <&iomuxc_gpio1_io05_gpio_io_gpio1_io5>, + <&iomuxc_gpio1_io06_gpio_io_gpio1_io6>, + <&iomuxc_gpio1_io07_gpio_io_gpio1_io7>, + <&iomuxc_gpio1_io08_gpio_io_gpio1_io8>, + <&iomuxc_gpio1_io09_gpio_io_gpio1_io9>, + <&iomuxc_gpio1_io10_gpio_io_gpio1_io10>, + <&iomuxc_gpio1_io11_gpio_io_gpio1_io11>, + <&iomuxc_gpio1_io12_gpio_io_gpio1_io12>, + <&iomuxc_gpio1_io13_gpio_io_gpio1_io13>, + <&iomuxc_gpio1_io14_gpio_io_gpio1_io14>, + <&iomuxc_gpio1_io15_gpio_io_gpio1_io15>, + <&iomuxc_enet_mdc_gpio_io_gpio1_io16>, + <&iomuxc_enet_mdio_gpio_io_gpio1_io17>, + <&iomuxc_enet_td3_gpio_io_gpio1_io18>, + <&iomuxc_enet_td2_gpio_io_gpio1_io19>, + <&iomuxc_enet_td1_gpio_io_gpio1_io20>, + <&iomuxc_enet_td0_gpio_io_gpio1_io21>, + <&iomuxc_enet_tx_ctl_gpio_io_gpio1_io22>, + <&iomuxc_enet_txc_gpio_io_gpio1_io23>, + <&iomuxc_enet_rx_ctl_gpio_io_gpio1_io24>, + <&iomuxc_enet_rxc_gpio_io_gpio1_io25>, + <&iomuxc_enet_rd0_gpio_io_gpio1_io26>, + <&iomuxc_enet_rd1_gpio_io_gpio1_io27>, + <&iomuxc_enet_rd2_gpio_io_gpio1_io28>, + <&iomuxc_enet_rd3_gpio_io_gpio1_io29>; +}; + +&gpio2{ + pinmux = <&iomuxc_sd1_clk_gpio_io_gpio2_io0>, + <&iomuxc_sd1_cmd_gpio_io_gpio2_io1>, + <&iomuxc_sd1_data0_gpio_io_gpio2_io2>, + <&iomuxc_sd1_data1_gpio_io_gpio2_io3>, + <&iomuxc_sd1_data2_gpio_io_gpio2_io4>, + <&iomuxc_sd1_data3_gpio_io_gpio2_io5>, + <&iomuxc_sd1_data4_gpio_io_gpio2_io6>, + <&iomuxc_sd1_data5_gpio_io_gpio2_io7>, + <&iomuxc_sd1_data6_gpio_io_gpio2_io8>, + <&iomuxc_sd1_data7_gpio_io_gpio2_io9>, + <&iomuxc_sd1_reset_b_gpio_io_gpio2_io10>, + <&iomuxc_sd1_strobe_gpio_io_gpio2_io11>, + <&iomuxc_sd2_cd_b_gpio_io_gpio2_io12>, + <&iomuxc_sd2_clk_gpio_io_gpio2_io13>, + <&iomuxc_sd2_cmd_gpio_io_gpio2_io14>, + <&iomuxc_sd2_data0_gpio_io_gpio2_io15>, + <&iomuxc_sd2_data1_gpio_io_gpio2_io16>, + <&iomuxc_sd2_data2_gpio_io_gpio2_io17>, + <&iomuxc_sd2_data3_gpio_io_gpio2_io18>, + <&iomuxc_sd2_reset_b_gpio_io_gpio2_io19>, + <&iomuxc_sd2_wp_gpio_io_gpio2_io20>; +}; + +&gpio3{ + pinmux = <&iomuxc_nand_ale_gpio_io_gpio3_io0>, + <&iomuxc_nand_ce0_b_gpio_io_gpio3_io1>, + <&iomuxc_nand_ce1_b_gpio_io_gpio3_io2>, + <&iomuxc_nand_ce2_b_gpio_io_gpio3_io3>, + <&iomuxc_nand_ce3_b_gpio_io_gpio3_io4>, + <&iomuxc_nand_cle_gpio_io_gpio3_io5>, + <&iomuxc_nand_data00_gpio_io_gpio3_io6>, + <&iomuxc_nand_data01_gpio_io_gpio3_io7>, + <&iomuxc_nand_data02_gpio_io_gpio3_io8>, + <&iomuxc_nand_data03_gpio_io_gpio3_io9>, + <&iomuxc_nand_data04_gpio_io_gpio3_io10>, + <&iomuxc_nand_data05_gpio_io_gpio3_io11>, + <&iomuxc_nand_data06_gpio_io_gpio3_io12>, + <&iomuxc_nand_data07_gpio_io_gpio3_io13>, + <&iomuxc_nand_dqs_gpio_io_gpio3_io14>, + <&iomuxc_nand_re_b_gpio_io_gpio3_io15>, + <&iomuxc_nand_ready_b_gpio_io_gpio3_io16>, + <&iomuxc_nand_we_b_gpio_io_gpio3_io17>, + <&iomuxc_nand_wp_b_gpio_io_gpio3_io18>, + <&iomuxc_sai5_rxfs_gpio_io_gpio3_io19>, + <&iomuxc_sai5_rxc_gpio_io_gpio3_io20>, + <&iomuxc_sai5_rxd0_gpio_io_gpio3_io21>, + <&iomuxc_sai5_rxd1_gpio_io_gpio3_io22>, + <&iomuxc_sai5_rxd2_gpio_io_gpio3_io23>, + <&iomuxc_sai5_rxd3_gpio_io_gpio3_io24>, + <&iomuxc_sai5_mclk_gpio_io_gpio3_io25>, + <&iomuxc_hdmi_ddc_scl_gpio_io_gpio3_io26>, + <&iomuxc_hdmi_ddc_sda_gpio_io_gpio3_io27>, + <&iomuxc_hdmi_cec_gpio_io_gpio3_io28>, + <&iomuxc_hdmi_hpd_gpio_io_gpio3_io29>; +}; + +&gpio4{ + pinmux = <&iomuxc_sai1_rxfs_gpio_io_gpio4_io0>, + <&iomuxc_sai1_rxc_gpio_io_gpio4_io1>, + <&iomuxc_sai1_rxd0_gpio_io_gpio4_io2>, + <&iomuxc_sai1_rxd1_gpio_io_gpio4_io3>, + <&iomuxc_sai1_rxd2_gpio_io_gpio4_io4>, + <&iomuxc_sai1_rxd3_gpio_io_gpio4_io5>, + <&iomuxc_sai1_rxd4_gpio_io_gpio4_io6>, + <&iomuxc_sai1_rxd5_gpio_io_gpio4_io7>, + <&iomuxc_sai1_rxd6_gpio_io_gpio4_io8>, + <&iomuxc_sai1_rxd7_gpio_io_gpio4_io9>, + <&iomuxc_sai1_txfs_gpio_io_gpio4_io10>, + <&iomuxc_sai1_txc_gpio_io_gpio4_io11>, + <&iomuxc_sai1_txd0_gpio_io_gpio4_io12>, + <&iomuxc_sai1_txd1_gpio_io_gpio4_io13>, + <&iomuxc_sai1_txd2_gpio_io_gpio4_io14>, + <&iomuxc_sai1_txd3_gpio_io_gpio4_io15>, + <&iomuxc_sai1_txd4_gpio_io_gpio4_io16>, + <&iomuxc_sai1_txd5_gpio_io_gpio4_io17>, + <&iomuxc_sai1_txd6_gpio_io_gpio4_io18>, + <&iomuxc_sai1_txd7_gpio_io_gpio4_io19>, + <&iomuxc_sai1_mclk_gpio_io_gpio4_io20>, + <&iomuxc_sai2_rxfs_gpio_io_gpio4_io21>, + <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>, + <&iomuxc_sai2_rxd0_gpio_io_gpio4_io23>, + <&iomuxc_sai2_txfs_gpio_io_gpio4_io24>, + <&iomuxc_sai2_txc_gpio_io_gpio4_io25>, + <&iomuxc_sai2_txd0_gpio_io_gpio4_io26>, + <&iomuxc_sai2_mclk_gpio_io_gpio4_io27>, + <&iomuxc_sai3_rxfs_gpio_io_gpio4_io28>, + <&iomuxc_sai3_rxc_gpio_io_gpio4_io29>, + <&iomuxc_sai3_rxd_gpio_io_gpio4_io30>, + <&iomuxc_sai3_txfs_gpio_io_gpio4_io31>; +}; + +&gpio5{ + pinmux = <&iomuxc_sai3_txc_gpio_io_gpio5_io0>, + <&iomuxc_sai3_txd_gpio_io_gpio5_io1>, + <&iomuxc_sai3_mclk_gpio_io_gpio5_io2>, + <&iomuxc_spdif_tx_gpio_io_gpio5_io3>, + <&iomuxc_spdif_rx_gpio_io_gpio5_io4>, + <&iomuxc_spdif_ext_clk_gpio_io_gpio5_io5>, + <&iomuxc_ecspi1_sclk_gpio_io_gpio5_io6>, + <&iomuxc_ecspi1_mosi_gpio_io_gpio5_io7>, + <&iomuxc_ecspi1_miso_gpio_io_gpio5_io8>, + <&iomuxc_ecspi1_ss0_gpio_io_gpio5_io9>, + <&iomuxc_ecspi2_sclk_gpio_io_gpio5_io10>, + <&iomuxc_ecspi2_mosi_gpio_io_gpio5_io11>, + <&iomuxc_ecspi2_miso_gpio_io_gpio5_io12>, + <&iomuxc_ecspi2_ss0_gpio_io_gpio5_io13>, + <&iomuxc_i2c1_scl_gpio_io_gpio5_io14>, + <&iomuxc_i2c1_sda_gpio_io_gpio5_io15>, + <&iomuxc_i2c2_scl_gpio_io_gpio5_io16>, + <&iomuxc_i2c2_sda_gpio_io_gpio5_io17>, + <&iomuxc_i2c3_scl_gpio_io_gpio5_io18>, + <&iomuxc_i2c3_sda_gpio_io_gpio5_io19>, + <&iomuxc_i2c4_scl_gpio_io_gpio5_io20>, + <&iomuxc_i2c4_sda_gpio_io_gpio5_io21>, + <&iomuxc_uart1_rxd_gpio_io_gpio5_io22>, + <&iomuxc_uart1_txd_gpio_io_gpio5_io23>, + <&iomuxc_uart2_rxd_gpio_io_gpio5_io24>, + <&iomuxc_uart2_txd_gpio_io_gpio5_io25>, + <&iomuxc_uart3_rxd_gpio_io_gpio5_io26>, + <&iomuxc_uart3_txd_gpio_io_gpio5_io27>, + <&iomuxc_uart4_rxd_gpio_io_gpio5_io28>, + <&iomuxc_uart4_txd_gpio_io_gpio5_io29>; +}; diff --git a/dts/bindings/pinctrl/nxp,imx8mp-pinctrl.yaml b/dts/bindings/pinctrl/nxp,imx8mp-pinctrl.yaml new file mode 100644 index 00000000000..374d5fa0205 --- /dev/null +++ b/dts/bindings/pinctrl/nxp,imx8mp-pinctrl.yaml @@ -0,0 +1,94 @@ +# Copyright (c) 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: | + The node has the 'pinctrl' node label set in MCUX SoC's devicetree. These + nodes can be autogenerated using the MCUXpresso config tools combined with + the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg + fields in a group select the pins to be configured, and the remaining + devicetree properties set configuration values for those pins + for example, here is an group configuring LPUART1 pins: + + group0 { + pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx:, + &iomuxc_uart4_txd_uart_tx_uart4_tx>; + bias-pull-up; + slew-rate = "slow"; + drive-strength = "x1"; + }; + + This will select UART4_RXD as UART4 rx, and UART4_TXD as UART4 tx. + Both pins will be configured with a slow slew rate, and minimum drive + strength. + Note that the soc level iomuxc dts file can be examined to find the possible + pinmux options. Here are the affects of each property on the + IOMUXC SW_PAD_CTL register: + input-schmitt-enable: HYS=1 + bias-pull-up: PUE=1, PE=1 + bias-pull-down: PUE=0, PE=1 + drive-open-drain: ODE=1 + slew-rate: FSEL= + drive-strength: DSE= + input-enable: SION=1 (in SW_MUX_CTL_PAD register) + + If only required properties are supplied, the pin will have the following + configuration: + HYS=0, + PE=0 + PUE=0 + ODE=0, + SRE=, + DSE=, + SION=0, + + +compatible: "nxp,imx8mp-pinctrl" + +include: + - name: base.yaml + - name: pincfg-node-group.yaml + child-binding: + child-binding: + property-allowlist: + - input-schmitt-enable + - drive-open-drain + - input-enable + - bias-pull-up + - bias-pull-down + +child-binding: + description: iMX pin controller pin group + child-binding: + description: | + iMX pin controller pin configuration node. + properties: + pinmux: + required: true + type: phandles + description: | + Pin mux selections for this group. See the soc level iomuxc DTSI file + for a defined list of these options. + drive-strength: + required: true + type: string + enum: + - "x1" + - "x4" + - "x2" + - "x6" + description: | + Pin output drive strength. Sets the DSE field in the IOMUXC peripheral. + 00 X1- low drive strength + 01 X4- high drive strength + 10 X2- medium drive strength + 11 X6- max drive strength + slew-rate: + required: true + type: string + enum: + - "slow" + - "fast" + description: | + Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral + 0 SLOW — Slow Frequency Slew Rate + 1 FAST — Fast Frequency Slew Rate diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.series b/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.series index 3a14d299db7..d7ac00d1bdf 100644 --- a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.series +++ b/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.series @@ -17,6 +17,10 @@ config GPIO_MCUX_IGPIO default y if HAS_MCUX_IGPIO depends on GPIO +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + source "soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.mimx8ml8_m7" endif # SOC_SERIES_IMX8ML_M7 diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.soc b/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.soc index 43572f1a047..224a112a67f 100644 --- a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.soc +++ b/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.soc @@ -16,6 +16,7 @@ config SOC_MIMX8ML8 select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS select ARM_MPU select HAS_MCUX_IGPIO + select HAS_MCUX_IOMUXC endchoice diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/pinctrl_soc.h b/soc/arm/nxp_imx/mimx8ml8_m7/pinctrl_soc.h new file mode 100644 index 00000000000..f047cb546bf --- /dev/null +++ b/soc/arm/nxp_imx/mimx8ml8_m7/pinctrl_soc.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2022, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM_NXP_MIMX8ML8_M7_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_NXP_MIMX8ML8_M7_PINCTRL_SOC_H_ + +#include +#include +#include "fsl_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT +#define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT +#define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT +#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT +#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT +#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT +#define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */ +#define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1) + +#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id) \ + ((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) | \ + (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) | \ + ((DT_PROP(node_id, bias_pull_up) | DT_PROP(node_id, bias_pull_down)) \ + << MCUX_IMX_BIAS_PULL_ENABLE_SHIFT) | \ + (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \ + (DT_ENUM_IDX(node_id, drive_strength) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) | \ + (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) | \ + (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT)) + + +/* This struct must be present. It is used by the mcux gpio driver */ +struct pinctrl_soc_pinmux { + uint32_t mux_register; /*!< IOMUXC SW_PAD_MUX register */ + uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */ + uint32_t input_register; /*!< IOMUXC SELECT_INPUT DAISY register */ + uint8_t mux_mode: 4; /*!< Mux value for SW_PAD_MUX register */ + uint32_t input_daisy:4; /*!< Mux value for SELECT_INPUT_DAISY register */ +}; + +struct pinctrl_soc_pin { + struct pinctrl_soc_pinmux pinmux; + uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */ +}; + +typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; + +/* This definition must be present. It is used by the mcux gpio driver */ +#define MCUX_IMX_PINMUX(node_id) \ + { \ + .mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .config_register = DT_PROP_BY_IDX(node_id, pinmux, 4), \ + .input_register = DT_PROP_BY_IDX(node_id, pinmux, 2), \ + .mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1), \ + .input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3), \ + } + +#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx) \ + MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx)) + +#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx) \ + { \ + .pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx), \ + .pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id), \ + }, + + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ + DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)}; \ + + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_NXP_MIMX8ML8_M7_PINCTRL_SOC_H_ */