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board: arc: hsdk*: Accommodate upstream OpenOCD for ARC

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During review of ARC port of OpenOCD some changes were requested
in particular:
1. L2 cache (SLC in ARC parlance) semantics, see
   http://openocd.zylin.com/#/c/5688/

2. JTAG probe interface (AKA "adapter") setup, see
   http://openocd.zylin.com/#/c/5784/

And so we need to change OpenOCD scripts accordingly to match
newer OpenOCD version from Zephyr's SDK v0.12.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Alexey Brodkin 2020-11-26 17:17:49 +03:00 • committed by Anas Nashif
commit de668aa692
2 changed files with 11 additions and 12 deletions
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8
boards/arc/hsdk/support/openocd-2-cores.cfg
View file

@ -5,7 +5,7 @@
# Configure JTAG cable # Configure JTAG cable
# SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that # SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that
# it uses channgel B for JTAG, instead of channel A. # it uses channgel B for JTAG, instead of channel A.
interface ftdi adapter driver ftdi
# Only specify FTDI serial number if it is specified via # Only specify FTDI serial number if it is specified via
# "set _ZEPHYR_BOARD_SERIAL 12345" before reading this script # "set _ZEPHYR_BOARD_SERIAL 12345" before reading this script
@ -18,7 +18,7 @@ ftdi_layout_init 0x0088 0x008b
ftdi_channel 1 ftdi_channel 1
adapter_khz 10000 adapter speed 10000
# ARCs supports only JTAG. # ARCs supports only JTAG.
transport select jtag transport select jtag
@ -59,7 +59,7 @@ set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
arc_hs_init_regs arc_hs_init_regs
# Enable L2 cache support for core 2. # Enable L2 cache support for core 2.
$_TARGETNAME2 arc has-l2cache true $_TARGETNAME2 arc cache l2 auto 1
################################ ################################
# ARC HS38 core 1 # ARC HS38 core 1
@ -74,7 +74,7 @@ set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
arc_hs_init_regs arc_hs_init_regs
# Enable L2 cache support for core 1. # Enable L2 cache support for core 1.
$_TARGETNAME1 arc has-l2cache true $_TARGETNAME1 arc cache l2 auto 1
target smp $_TARGETNAME1 $_TARGETNAME2 target smp $_TARGETNAME1 $_TARGETNAME2

15
boards/arc/hsdk/support/openocd.cfg
View file

@ -1,11 +1,11 @@
# Copyright (C) 2019 Synopsys, Inc. # Copyright (C) 2019-2020 Synopsys, Inc.
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
# #
# Configure JTAG cable # Configure JTAG cable
# SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that # SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that
# it uses channgel B for JTAG, instead of channel A. # it uses channgel B for JTAG, instead of channel A.
interface ftdi adapter driver ftdi
# Only specify FTDI serial number if it is specified via # Only specify FTDI serial number if it is specified via
# "set _ZEPHYR_BOARD_SERIAL 12345" before reading this script # "set _ZEPHYR_BOARD_SERIAL 12345" before reading this script
@ -18,7 +18,7 @@ ftdi_layout_init 0x0088 0x008b
ftdi_channel 1 ftdi_channel 1
adapter_khz 10000 adapter speed 10000
# ARCs supports only JTAG. # ARCs supports only JTAG.
transport select jtag transport select jtag
@ -63,8 +63,7 @@ set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
arc_hs_init_regs arc_hs_init_regs
# Enable L2 cache support for core 2. # Enable L2 cache support for core 2.
$_TARGETNAME2 arc has-l2cache true $_TARGETNAME2 arc cache l2 auto 1
################################ ################################
# ARC HS38 core 3 # ARC HS38 core 3
@ -79,7 +78,7 @@ set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
arc_hs_init_regs arc_hs_init_regs
# Enable L2 cache support for core 3. # Enable L2 cache support for core 3.
$_TARGETNAME3 arc has-l2cache true $_TARGETNAME3 arc cache l2 auto 1
################################ ################################
# ARC HS38 core 4 # ARC HS38 core 4
@ -95,7 +94,7 @@ set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
arc_hs_init_regs arc_hs_init_regs
# Enable L2 cache support for core 4. # Enable L2 cache support for core 4.
$_TARGETNAME4 arc has-l2cache true $_TARGETNAME4 arc cache l2 auto 1
################################ ################################
# ARC HS38 core 1 # ARC HS38 core 1
@ -110,7 +109,7 @@ set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
arc_hs_init_regs arc_hs_init_regs
# Enable L2 cache support for core 1. # Enable L2 cache support for core 1.
$_TARGETNAME1 arc has-l2cache true $_TARGETNAME1 arc cache l2 auto 1
target smp $_TARGETNAME1 $_TARGETNAME2 $_TARGETNAME3 $_TARGETNAME4 target smp $_TARGETNAME1 $_TARGETNAME2 $_TARGETNAME3 $_TARGETNAME4