dts: bindings: add bindings for the Xilinx AXI Timer

Add devicetree bindings for the Xilinx AXI Timer IP. This timer can
either be used as a counter or as a PWM controller.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>

dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml

@@ -0,0 +1,71 @@
+description: Xilinx AXI Timer IP node
+
+compatible: "xlnx,xps-timer-1.00.a"
+
+include: rtc.yaml
+
+# Property names correspond to those used by Xilinx PetaLinux:
+# https://github.com/Xilinx/meta-xilinx
+
+properties:
+    clock-frequency:
+      required: true
+
+    xlnx,count-width:
+      type: int
+      required: true
+      enum:
+        - 8
+        - 16
+        - 32
+      description: |
+        Individual timer/counter width in bits.
+
+    xlnx,gen0-assert:
+      type: int
+      required: false
+      enum:
+        - 0
+        - 1
+      description: |
+        Active state of the generateout0 signal (0 for active-low, 1 for
+        active-high).
+
+    xlnx,gen1-assert:
+      type: int
+      required: false
+      enum:
+        - 0
+        - 1
+      description: |
+        Active state of the generateout1 signal (0 for active-low, 1 for
+        active-high).
+
+    xlnx,one-timer-only:
+      type: int
+      required: true
+      enum:
+        - 0
+        - 1
+      description: |
+        0 if both Timer 1 and Timer 2 are enabled, 1 if only Timer 1 is enabled.
+
+    xlnx,trig0-assert:
+      type: int
+      required: false
+      enum:
+        - 0
+        - 1
+      description: |
+        Active state of the capturetrig0 signal (0 for active-low, 1 for
+        active-high).
+
+    xlnx,trig1-assert:
+      type: int
+      required: false
+      enum:
+        - 0
+        - 1
+      description: |
+        Active state of the capturetrig1 signal (0 for active-low, 1 for
+        active-high).