From de49dac73894480b877539250235f58ecd9cf874 Mon Sep 17 00:00:00 2001 From: Tien Nguyen Date: Tue, 4 Mar 2025 15:58:38 +0700 Subject: [PATCH] soc: renesas: Add initial support for Renesas RZ/G2L Add initial support for Renesas RZ/G2L Signed-off-by: Tien Nguyen Signed-off-by: Nhut Nguyen --- soc/renesas/rz/rzg2l/CMakeLists.txt | 8 ++++++++ soc/renesas/rz/rzg2l/Kconfig | 10 ++++++++++ soc/renesas/rz/rzg2l/Kconfig.defconfig | 24 ++++++++++++++++++++++++ soc/renesas/rz/rzg2l/Kconfig.soc | 24 ++++++++++++++++++++++++ soc/renesas/rz/rzg2l/pinctrl_soc.h | 11 +++++++++++ soc/renesas/rz/rzg2l/soc.c | 21 +++++++++++++++++++++ soc/renesas/rz/rzg2l/soc.h | 12 ++++++++++++ soc/renesas/rz/soc.yml | 5 +++++ 8 files changed, 115 insertions(+) create mode 100644 soc/renesas/rz/rzg2l/CMakeLists.txt create mode 100644 soc/renesas/rz/rzg2l/Kconfig create mode 100644 soc/renesas/rz/rzg2l/Kconfig.defconfig create mode 100644 soc/renesas/rz/rzg2l/Kconfig.soc create mode 100644 soc/renesas/rz/rzg2l/pinctrl_soc.h create mode 100644 soc/renesas/rz/rzg2l/soc.c create mode 100644 soc/renesas/rz/rzg2l/soc.h diff --git a/soc/renesas/rz/rzg2l/CMakeLists.txt b/soc/renesas/rz/rzg2l/CMakeLists.txt new file mode 100644 index 00000000000..a58ca9b77f5 --- /dev/null +++ b/soc/renesas/rz/rzg2l/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rz/rzg2l/Kconfig b/soc/renesas/rz/rzg2l/Kconfig new file mode 100644 index 00000000000..fa2ec4ab067 --- /dev/null +++ b/soc/renesas/rz/rzg2l/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZG2L + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select HAS_RENESAS_RZ_FSP + select CPU_CORTEX_M_HAS_DWT + select SOC_EARLY_INIT_HOOK diff --git a/soc/renesas/rz/rzg2l/Kconfig.defconfig b/soc/renesas/rz/rzg2l/Kconfig.defconfig new file mode 100644 index 00000000000..bfde46db7e1 --- /dev/null +++ b/soc/renesas/rz/rzg2l/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RZG2L + +config NUM_IRQS + default 480 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config SYS_CLOCK_EXISTS + default y + +config INIT_ARCH_HW_AT_BOOT + default y + +endif # SOC_SERIES_RZG2L diff --git a/soc/renesas/rz/rzg2l/Kconfig.soc b/soc/renesas/rz/rzg2l/Kconfig.soc new file mode 100644 index 00000000000..07673b66d4a --- /dev/null +++ b/soc/renesas/rz/rzg2l/Kconfig.soc @@ -0,0 +1,24 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZG2L + bool + select SOC_FAMILY_RENESAS_RZ + help + Renesas RZ/G2L series + +config SOC_SERIES + default "rzg2l" if SOC_SERIES_RZG2L + +config SOC_R9A07G044L23GBG + bool + select SOC_SERIES_RZG2L + help + R9A07G044L23GBG + +config SOC_R9A07G044L23GBG_CM33 + bool + select SOC_R9A07G044L23GBG + +config SOC + default "r9a07g044l23gbg" if SOC_R9A07G044L23GBG diff --git a/soc/renesas/rz/rzg2l/pinctrl_soc.h b/soc/renesas/rz/rzg2l/pinctrl_soc.h new file mode 100644 index 00000000000..cd19f259325 --- /dev/null +++ b/soc/renesas/rz/rzg2l/pinctrl_soc.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZ_RZG2L_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZ_RZG2L_PINCTRL_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZ_RZG2L_PINCTRL_SOC_H_ */ diff --git a/soc/renesas/rz/rzg2l/soc.c b/soc/renesas/rz/rzg2l/soc.c new file mode 100644 index 00000000000..2418462b14a --- /dev/null +++ b/soc/renesas/rz/rzg2l/soc.c @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RZ/G2L Group + */ + +#include +#include + +/* System core clock is set to 200 MHz after reset */ +uint32_t SystemCoreClock = 200000000; + +void soc_early_init_hook(void) +{ + bsp_clock_init(); +} diff --git a/soc/renesas/rz/rzg2l/soc.h b/soc/renesas/rz/rzg2l/soc.h new file mode 100644 index 00000000000..20cdc8fd15a --- /dev/null +++ b/soc/renesas/rz/rzg2l/soc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZG2L_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZG2L_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZG2L_SOC_H_ */ diff --git a/soc/renesas/rz/soc.yml b/soc/renesas/rz/soc.yml index 1336fb27de9..446b8edcca8 100644 --- a/soc/renesas/rz/soc.yml +++ b/soc/renesas/rz/soc.yml @@ -4,6 +4,11 @@ family: - name: rza3ul socs: - name: r9a07g063u02gbg + - name: rzg2l + socs: + - name: r9a07g044l23gbg + cpuclusters: + - name: cm33 - name: rzg3s socs: - name: r9a08g045s33gbg