nxp_kinetis: Refactor K64F init to use ksdk clock driver
The ksdk provides a clock driver, fsl_clock.c, for the K64F and an example usage of that driver, clock_config.c, for the Freedom board. See ext/hal/ksdk/devices/MK64F12/ Leverage parts of clock_config.c to configure the clocks (specifically, the sequence in BOARD_BootClockRUN()), but use the new Kconfig options to set up the configuration structure. This will allow support for new boards that may have a different external oscillator frequency or type. Jira: ZEP-715 Change-Id: I3f0c75e6236f57600cd8b7f06f4482b13026fc10 Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm
parent
4b554baa87
commit
de2a471138
1 changed files with 52 additions and 162 deletions
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@ -30,27 +30,16 @@
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#include <uart.h>
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#include <sections.h>
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#include <fsl_common.h>
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#include <fsl_clock.h>
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#include <arch/cpu.h>
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#define PLLFLLSEL_MCGFLLCLK (0)
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#define PLLFLLSEL_MCGPLLCLK (1)
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#define PLLFLLSEL_IRC48MHZ (3)
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/* board's setting for PLL multipler (PRDIV0) */
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#define FRDM_K64F_PLL_DIV_20 (20 - 1)
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/* board's setting for PLL multipler (VDIV0) */
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#define FRDM_K64F_PLL_MULT_48 (48 - 24)
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/* MCG register field encodings */
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#define MCG_C1_CLKS_FLL_PLL (MCG_C1_CLKS(0))
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#define MCG_C1_CLKS_EXT_REF (MCG_C1_CLKS(2))
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#define MCG_C1_FRDIV_32_1024 (MCG_C1_FRDIV(5))
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#define MCG_C1_IREFS_EXT (MCG_C1_IREFS(0))
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#define MCG_C2_RANGE_VHIGH (MCG_C2_RANGE(2))
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#define MCG_C2_HGO_LO_PWR (MCG_C2_HGO(0))
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#define MCG_C2_EREFS_EXT_CLK (MCG_C2_EREFS(0))
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#define MCG_C6_PLLS_PLL (MCG_C6_PLLS(1))
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#define MCG_C7_OSCSEL_OSC0 (MCG_C7_OSCSEL(0))
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#define MCG_S_CLKST_EXT_REF (MCG_S_CLKST(2))
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#define MCG_S_CLKST_PLL (MCG_S_CLKST(3))
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#define ER32KSEL_OSC32KCLK (0)
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#define ER32KSEL_RTC (2)
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#define ER32KSEL_LPO1KHZ (3)
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/*
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* K64F Flash configuration fields
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@ -83,6 +72,44 @@ uint8_t __security_frdm_k64f_section __security_frdm_k64f[] = {
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/* Reserved for FlexNVM feature (unsupported by this MCU) */
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0xFF, 0xFF};
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static const osc_config_t oscConfig = {
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.freq = CONFIG_OSC_XTAL0_FREQ,
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.capLoad = 0,
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#if defined(CONFIG_OSC_EXTERNAL)
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.workMode = kOSC_ModeExt,
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#elif defined(CONFIG_OSC_LOW_POWER)
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.workMode = kOSC_ModeOscLowPower,
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#elif defined(CONFIG_OSC_HIGH_GAIN)
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.workMode = kOSC_ModeOscHighGain,
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#else
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#error "An oscillator mode must be defined"
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#endif
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.oscerConfig = {
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.enableMode = kOSC_ErClkEnable,
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#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
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FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
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.erclkDiv = 0U,
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#endif
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},
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};
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static const mcg_pll_config_t pll0Config = {
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.enableMode = 0U,
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.prdiv = CONFIG_MCG_PRDIV0,
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.vdiv = CONFIG_MCG_VDIV0,
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};
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static const sim_clock_config_t simConfig = {
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.pllFllSel = PLLFLLSEL_MCGPLLCLK, /* PLLFLLSEL select PLL. */
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.er32kSrc = ER32KSEL_RTC, /* ERCLK32K selection, use RTC. */
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_K64_CORE_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV2(CONFIG_K64_BUS_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV3(CONFIG_K64_FLEXBUS_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV4(CONFIG_K64_FLASH_CLOCK_DIVIDER - 1),
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};
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/**
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*
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* @brief Initialize the system clock
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@ -99,143 +126,19 @@ uint8_t __security_frdm_k64f_section __security_frdm_k64f[] = {
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* @return N/A
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*
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*/
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static ALWAYS_INLINE void clkInit(void)
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{
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uint8_t temp_reg;
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CLOCK_SetSimSafeDivs();
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/*
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* Select the 50 Mhz external clock as the MCG OSC clock.
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* MCG Control 7 register:
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* - Select OSCCLK0 / XTAL
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*/
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CLOCK_InitOsc0(&oscConfig);
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CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
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temp_reg = MCG->C7 & ~MCG_C7_OSCSEL_MASK;
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temp_reg |= MCG_C7_OSCSEL_OSC0;
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MCG->C7 = temp_reg;
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CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
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/*
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* Transition MCG from FEI mode (at reset) to FBE mode.
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*/
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CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
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CONFIG_MCG_FCRDIV);
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/*
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* MCG Control 2 register:
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* - Set oscillator frequency range = very high for 50 MHz external
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* clock
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* - Set oscillator mode = low power
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* - Select external reference clock as the oscillator source
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*/
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temp_reg = MCG->C2 &
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~(MCG_C2_RANGE_MASK | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK);
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temp_reg |=
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(MCG_C2_RANGE_VHIGH | MCG_C2_HGO_LO_PWR | MCG_C2_EREFS_EXT_CLK);
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MCG->C2 = temp_reg;
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/*
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* MCG Control 1 register:
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* - Set system clock source (MCGOUTCLK) = external reference clock
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* - Set FLL external reference divider = 1024 (MCG_C1_FRDIV_32_1024)
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* to get the FLL frequency of 50 MHz/1024 = 48.828KHz
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* (Note: If FLL frequency must be in the in 31.25KHz-39.0625KHz
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*range,
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* the FLL external reference divider = 1280
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*(MCG_C1_FRDIV_64_1280)
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* to get 50 MHz/1280 = 39.0625KHz)
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* - Select the external reference clock as the FLL reference source
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*
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*/
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temp_reg = MCG->C1 &
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~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK);
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temp_reg |=
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(MCG_C1_CLKS_EXT_REF | MCG_C1_FRDIV_32_1024 | MCG_C1_IREFS_EXT);
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MCG->C1 = temp_reg;
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/*
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* Confirm that the external reference clock is the FLL reference
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* source
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*/
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while ((MCG->S & MCG_S_IREFST_MASK) != 0)
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;
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;
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/*
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* Confirm the external ref. clock is the system clock source
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* (MCGOUTCLK)
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*/
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while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXT_REF)
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;
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;
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/*
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* Transition to PBE mode.
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* Configure the PLL frequency in preparation for PEE mode.
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* The goal is PEE mode with a 120 MHz system clock source (MCGOUTCLK),
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* which is calculated as (oscillator clock / PLL divider) * PLL
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* multiplier,
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* where oscillator clock = 50MHz, PLL divider = 20 and PLL multiplier =
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* 48.
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*/
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/*
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* MCG Control 5 register:
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* - Set the PLL divider
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*/
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temp_reg = MCG->C5 & ~MCG_C5_PRDIV0_MASK;
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temp_reg |= FRDM_K64F_PLL_DIV_20;
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MCG->C5 = temp_reg;
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/*
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* MCG Control 6 register:
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* - Select PLL as output for PEE mode
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* - Set the PLL multiplier
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*/
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temp_reg = MCG->C6 & ~(MCG_C6_PLLS_MASK | MCG_C6_VDIV0_MASK);
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temp_reg |= (MCG_C6_PLLS_PLL | FRDM_K64F_PLL_MULT_48);
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MCG->C6 = temp_reg;
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/* Confirm that the PLL clock is selected as the PLL output */
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while ((MCG->S & MCG_S_PLLST_MASK) == 0)
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;
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;
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/* Confirm that the PLL has acquired lock */
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while ((MCG->S & MCG_S_LOCK0_MASK) == 0)
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;
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;
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/*
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* Transition to PEE mode.
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* MCG Control 1 register:
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* - Select PLL as the system clock source (MCGOUTCLK)
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*/
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temp_reg = MCG->C1 & ~MCG_C1_CLKS_MASK;
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temp_reg |= MCG_C1_CLKS_FLL_PLL;
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MCG->C1 = temp_reg;
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/* Confirm that the PLL output is the system clock source (MCGOUTCLK) */
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while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL)
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;
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;
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CLOCK_SetSimConfig(&simConfig);
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}
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/**
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@ -286,19 +189,6 @@ static int fsl_frdm_k64f_init(struct device *arg)
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_ScbHardFaultAllFaultsReset();
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/*
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* Initialize the clock dividers for:
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* core and system clocks = 120 MHz (PLL/OUTDIV1)
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* bus clock = 60 MHz (PLL/OUTDIV2)
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* FlexBus clock = 40 MHz (PLL/OUTDIV3)
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* Flash clock = 24 MHz (PLL/OUTDIV4)
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*/
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SIM->CLKDIV1 = (
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SIM_CLKDIV1_OUTDIV1(CONFIG_K64_CORE_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV2(CONFIG_K64_BUS_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV3(CONFIG_K64_FLEXBUS_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV4(CONFIG_K64_FLASH_CLOCK_DIVIDER - 1));
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/* Initialize PLL/system clock to 120 MHz */
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clkInit();
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