From de20a6558adf3dcb903fe2856265e6abdb4bcf4f Mon Sep 17 00:00:00 2001
From: Gil Pitney <gil.pitney@linaro.org>
Date: Tue, 18 Apr 2017 14:18:50 -0700
Subject: [PATCH] cc3200: Make use of mem.h file in soc dtsi file.

This in preparation for adding a cc3220sf DTS file, which
has a different address for sram0 than the cc3200.

Also moved baud-rate out of soc dtsi file to board dts.

Jira: JEP-1958

Change-Id: I641452c0a8a6d1ad4424e132d6ef2de71d8545b4
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
---
 dts/arm/cc3200_launchxl.dts                      |  5 +++--
 dts/arm/ti/{cc32xx_launchxl.dtsi => cc32xx.dtsi} |  9 ++++-----
 dts/arm/ti/mem.h                                 | 14 ++++++++++++++
 3 files changed, 21 insertions(+), 7 deletions(-)
 rename dts/arm/ti/{cc32xx_launchxl.dtsi => cc32xx.dtsi} (86%)
 create mode 100644 dts/arm/ti/mem.h

diff --git a/dts/arm/cc3200_launchxl.dts b/dts/arm/cc3200_launchxl.dts
index af4c6aee860..3e9dd4fee04 100644
--- a/dts/arm/cc3200_launchxl.dts
+++ b/dts/arm/cc3200_launchxl.dts
@@ -1,10 +1,10 @@
 /dts-v1/;
 
-#include <ti/cc32xx_launchxl.dtsi>
+#include <ti/cc32xx.dtsi>
 
 / {
 	model = "TI CC3200 LaunchXL";
-	compatible = "ti,cc32xx";
+	compatible = "ti,cc3200-launchxl","ti,cc3200","ti,cc32xx";
 
 	aliases {
 		uart_0 = &uart0;
@@ -19,4 +19,5 @@
 
 &uart0 {
 	status = "ok";
+	baud-rate = <115200>;
 };
diff --git a/dts/arm/ti/cc32xx_launchxl.dtsi b/dts/arm/ti/cc32xx.dtsi
similarity index 86%
rename from dts/arm/ti/cc32xx_launchxl.dtsi
rename to dts/arm/ti/cc32xx.dtsi
index 0254f647d8b..91c72460df1 100644
--- a/dts/arm/ti/cc32xx_launchxl.dtsi
+++ b/dts/arm/ti/cc32xx.dtsi
@@ -1,7 +1,8 @@
 #include <arm/armv7-m.dtsi>
 #include <inc/hw_ints.h>
+#include <ti/mem.h>
 
-/* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC3200 SDK */
+/* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC32XX SDK */
 /* which are offset by 16: */
 #define EXP_UARTA0 (INT_UARTA0 - 16)
 #define EXP_UARTA1 (INT_UARTA1 - 16)
@@ -15,12 +16,12 @@
 
 	sram0: memory {
 		compatible = "sram";
-		reg = <0x20004000 0x3C000>;
+		reg = <DT_SRAM_START DT_SRAM_SIZE>;
 	};
 
 	flash0: serial-flash {
 		compatible = "serial-flash";
-		reg = <0x0 0x80000>;
+		reg = <0x0 DT_SFLASH_SIZE>;
 	};
 
 	soc {
@@ -28,7 +29,6 @@
 			compatible = "ti,cc32xx-uart";
 			reg = <0x4000C000 0x4c>;
 			interrupts = <EXP_UARTA0 3>;
-			baud-rate = <115200>;
 			status = "disabled";
 		};
 
@@ -36,7 +36,6 @@
 			compatible = "ti,cc32xx-uart";
 			reg = <0x4000D000 0x4c>;
 			interrupts = <EXP_UARTA1 3>;
-			baud-rate = <115200>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/ti/mem.h b/dts/arm/ti/mem.h
new file mode 100644
index 00000000000..253b38fe470
--- /dev/null
+++ b/dts/arm/ti/mem.h
@@ -0,0 +1,14 @@
+#ifndef __DT_BINDING_TI_MEM_H
+#define __DT_BINDING_TI_MEM_H
+
+#define __SIZE_K(x) (x * 1024)
+
+#if defined(CONFIG_SOC_CC3200)
+#define DT_SFLASH_SIZE		__SIZE_K(1024)
+#define DT_SRAM_SIZE		__SIZE_K(240)
+#define DT_SRAM_START		0x20004000
+#else
+#error "Flash and RAM sizes not defined for this chip"
+#endif
+
+#endif /* __DT_BINDING_TI_MEM_H */