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dts: x86: Add device tree support for qemu_x86

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patch add device tree support for ia32 soc and qemu_x86
board port

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
This commit is contained in:
Savinay Dharmappa 2017-09-07 23:37:36 +05:30 • committed by Anas Nashif
commit ddf6a69577
8 changed files with 105 additions and 6 deletions
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6
arch/x86/soc/ia32/Kconfig.defconfig
View file

@ -11,12 +11,6 @@ if SOC_IA32
config SOC config SOC
default ia32 default ia32
config PHYS_LOAD_ADDR
default 0x00001000
config PHYS_RAM_ADDR
default 0x00400000
config RAM_SIZE config RAM_SIZE
default 4096 if XIP default 4096 if XIP
default 8188 if !XIP default 8188 if !XIP

1
arch/x86/soc/ia32/linker.ld
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@ -12,6 +12,7 @@
*/ */
#include <autoconf.h> #include <autoconf.h>
#include <generated_dts_board.h>
/* physical address where the kernel is loaded */ /* physical address where the kernel is loaded */
#define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR #define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR

1
boards/x86/qemu_x86/Kconfig.board
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@ -3,3 +3,4 @@ config BOARD_QEMU_X86
bool "QEMU x86" bool "QEMU x86"
depends on SOC_IA32 depends on SOC_IA32
select QEMU_TARGET select QEMU_TARGET
select HAS_DTS

1
dts/x86/Makefile
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@ -3,5 +3,6 @@ dtb-$(CONFIG_BOARD_ARDUINO_101) = arduino_101.dts_compiled
dtb-$(CONFIG_BOARD_QUARK_D2000_CRB) = quark_d2000_crb.dts_compiled dtb-$(CONFIG_BOARD_QUARK_D2000_CRB) = quark_d2000_crb.dts_compiled
dtb-$(CONFIG_BOARD_TINYTILE) = tinytile.dts_compiled dtb-$(CONFIG_BOARD_TINYTILE) = tinytile.dts_compiled
dtb-$(CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD) = quark_se_c1000_devboard.dts_compiled dtb-$(CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD) = quark_se_c1000_devboard.dts_compiled
dtb-$(CONFIG_BOARD_QEMU_X86) = qemu_x86.dts_compiled
always := $(dtb-y) always := $(dtb-y)
endif endif

51
dts/x86/ia32.dtsi Normal file
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@ -0,0 +1,51 @@
#include "skeleton.dtsi"
#include "mem.h"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "qemu32";
reg = <0>;
};
};
flash0: flash@00001000 {
reg = <0x00001000 DT_FLASH_SIZE>;
};
sram0: memory@00400000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x00400000 DT_SRAM_SIZE>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
uart0: uart@f0008000 {
compatible = "ns16550-uart";
reg = <0xf0008000 0x400>;
label = "UART_0";
status = "disabled";
};
uart1: uart@f0009000 {
compatible = "ns16550-uart";
reg = <0xf0009000 0x400>;
label = "UART_1";
status = "disabled";
};
};
};

7
dts/x86/mem.h
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@ -9,6 +9,13 @@
#elif defined(CONFIG_SOC_QUARK_D2000) #elif defined(CONFIG_SOC_QUARK_D2000)
#define DT_FLASH_SIZE __SIZE_K(32) #define DT_FLASH_SIZE __SIZE_K(32)
#define DT_SRAM_SIZE __SIZE_K(8) #define DT_SRAM_SIZE __SIZE_K(8)
#elif defined(CONFIG_SOC_IA32)
#define DT_FLASH_SIZE __SIZE_K(4092)
#if XIP
#define DT_SRAM_SIZE __SIZE_K(4096)
#else
#define DT_SRAM_SIZE __SIZE_K(8188)
#endif
#else #else
#error "Flash and RAM sizes not defined for this chip" #error "Flash and RAM sizes not defined for this chip"
#endif #endif

33
dts/x86/qemu_x86.dts Normal file
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@ -0,0 +1,33 @@
/dts-v1/;
#include <ia32.dtsi>
/ {
model = "QEMU X86";
compatible = "intel,ia32";
aliases {
uart_0 = &uart0;
uart_1 = &uart1;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,bt-uart = &uart1;
zephyr,uart-pipe = &uart1;
zephyr,bt-mon-uart = &uart1;
};
};
&uart0 {
status = "ok";
current-speed = <115200>;
};
&uart1 {
status = "ok";
current-speed = <115200>;
};

11
dts/x86/qemu_x86.fixup Normal file
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@ -0,0 +1,11 @@
#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE NS16550_UART_F0009000_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_1_NAME NS16550_UART_F0009000_LABEL
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_UART_F0008000_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_UART_F0008000_LABEL
#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS