From dd75bccaca74572173712935dddf96891a33ea66 Mon Sep 17 00:00:00 2001
From: Stephanos Ioannidis <root@stephanos.io>
Date: Wed, 18 Mar 2020 13:45:28 +0900
Subject: [PATCH] dts: bindings: Fix xlnx,ttcps binding compat

The `xlnx,ttcps` binding, despite having the file name of
`xlnx,ttcps.yaml`, had the compatible property of `cdns,ttc`.

While it is true that the Xilinx ZynqMP platform embeds the Cadence
Triple Timer Counter (TTC) IP core, its TTC differs from the original
Cadence core in that it implements 32-bit counters, instead of the
16-bit counters defined in the original; hence, the Xilinx variant is
not compatible with the original Cadence version and should be treated
as a different device.

This commit changes the `xlnx,ttcps.yaml` compatible property to
`xlnx,ttcps` for the above reasons.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
---
 dts/arm/xilinx/zynqmp.dtsi         | 8 ++++----
 dts/bindings/timer/xlnx,ttcps.yaml | 4 ++--
 tests/kernel/context/src/main.c    | 2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/dts/arm/xilinx/zynqmp.dtsi b/dts/arm/xilinx/zynqmp.dtsi
index fbfe2b775a2..8b733a804c3 100644
--- a/dts/arm/xilinx/zynqmp.dtsi
+++ b/dts/arm/xilinx/zynqmp.dtsi
@@ -31,7 +31,7 @@
 		};
 
 		ttc0: timer@ff110000 {
-			compatible = "cdns,ttc";
+			compatible = "xlnx,ttcps";
 			status = "disabled";
 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL
 					IRQ_DEFAULT_PRIORITY>,
@@ -45,7 +45,7 @@
 		};
 
 		ttc1: timer@ff120000 {
-			compatible = "cdns,ttc";
+			compatible = "xlnx,ttcps";
 			status = "disabled";
 			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL
 					IRQ_DEFAULT_PRIORITY>,
@@ -59,7 +59,7 @@
 		};
 
 		ttc2: timer@ff130000 {
-			compatible = "cdns,ttc";
+			compatible = "xlnx,ttcps";
 			status = "disabled";
 			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL
 					IRQ_DEFAULT_PRIORITY>,
@@ -73,7 +73,7 @@
 		};
 
 		ttc3: timer@ff140000 {
-			compatible = "cdns,ttc";
+			compatible = "xlnx,ttcps";
 			status = "disabled";
 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL
 					IRQ_DEFAULT_PRIORITY>,
diff --git a/dts/bindings/timer/xlnx,ttcps.yaml b/dts/bindings/timer/xlnx,ttcps.yaml
index 2803ec2b58e..b1aa3d4f203 100644
--- a/dts/bindings/timer/xlnx,ttcps.yaml
+++ b/dts/bindings/timer/xlnx,ttcps.yaml
@@ -1,6 +1,6 @@
 description: Xilinx ZynqMP PS TTC timer
 
-compatible: "cdns,ttc"
+compatible: "xlnx,ttcps"
 
 include: base.yaml
 
@@ -13,5 +13,5 @@ properties:
 
     clock-frequency:
       type: int
-      required: false
+      required: true
       description: Clock frequency information for Timer operation
diff --git a/tests/kernel/context/src/main.c b/tests/kernel/context/src/main.c
index eba12a3a004..a123ba8c129 100644
--- a/tests/kernel/context/src/main.c
+++ b/tests/kernel/context/src/main.c
@@ -70,7 +70,7 @@
 #elif defined(CONFIG_RV32M1_LPTMR_TIMER)
 #define TICK_IRQ DT_OPENISA_RV32M1_LPTMR_SYSTEM_LPTMR_IRQ_0
 #elif defined(CONFIG_XLNX_PSTTC_TIMER)
-#define TICK_IRQ DT_INST_0_CDNS_TTC_IRQ_0
+#define TICK_IRQ DT_INST_0_XLNX_TTCPS_IRQ_0
 #elif defined(CONFIG_CPU_CORTEX_M)
 /*
  * The Cortex-M use the SYSTICK exception for the system timer, which is