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arch: arm: cortex_a_r: add MPIDR and SG1R definition

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These definitions are required to be able to use GICv3
interrupts controller on an ARMv8 AArch32 processor.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
This commit is contained in:
Julien Massot 2022-01-27 14:37:41 +01:00 • committed by Carles Cufí
commit dd74db46e4
2 changed files with 44 additions and 1 deletions
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6
drivers/interrupt_controller/intc_gicv3.c
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@ -235,8 +235,12 @@ void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
/* Extract affinity fields from target */
aff1 = MPIDR_AFFLVL(target_aff, 1);
aff2 = MPIDR_AFFLVL(target_aff, 2);
#if defined(CONFIG_ARM)
/* There is no Aff3 in AArch32 MPIDR */
aff3 = 0;
#else
aff3 = MPIDR_AFFLVL(target_aff, 3);
#endif
sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id,
SGIR_IRM_TO_AFF, target_list);