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doc: ARC: update ARC HW & tools support status

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List of the changes:
 * add info about ARCv3 32bit HS5x which support has been
   upstreamed recently
 * mark HS6x MWDT toolchain support as Y

Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
This commit is contained in:
Evgeniy Paltsev 2022-05-11 18:17:04 +04:00 • committed by Carles Cufí
commit dd60d800d0
1 changed files with 52 additions and 54 deletions
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106
doc/hardware/arch/arc-support-status.rst
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@ -20,57 +20,57 @@ Legend:
**TBD** - to be decided **TBD** - to be decided
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| | **Processor families** | | | **Processor families** |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| | **EM** | **HS3x/4x** | **EV** | **HS6x** | | | **EM** | **HS3x/4x** | **EV** | **HS5x** | **HS6x** |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| Port status | upstreamed | upstreamed | WIP | upstreamed | | Port status | upstreamed | upstreamed | WIP | upstreamed | upstreamed |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| **Features** | | **Features** |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| Closely coupled memories (ICCM, DCCM) [#f1]_ | Y | Y | TBD | TBD | | Closely coupled memories (ICCM, DCCM) [#f1]_ | Y | Y | TBD | TBD | TBD |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| Execution with caches - Instruction/Data, L1/L2 caches | Y | Y | Y | Y | | Execution with caches - Instruction/Data, L1/L2 caches | Y | Y | Y | Y | Y |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| Hardware-assisted unaligned memory access | Y [#f2]_ | Y | TBD | Y | | Hardware-assisted unaligned memory access | Y [#f2]_ | Y | TBD | Y | Y |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| Regular interrupts with multiple priority levels, direct interrupts | Y | Y | TBD | Y | | Regular interrupts with multiple priority levels, direct interrupts | Y | Y | TBD | Y | Y |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| Fast interrupts, separate register banks for fast interrupts | Y | Y | TBD | N | | Fast interrupts, separate register banks for fast interrupts | Y | Y | TBD | N | N |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| Hardware floating point unit (FPU) | Y | Y | N | TBD | | Hardware floating point unit (FPU) | Y | Y | N | TBD | TBD |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| Symmetric multiprocessing (SMP) support, switch-based | N/A | Y | TBD | Y | | Symmetric multiprocessing (SMP) support, switch-based | N/A | Y | TBD | Y | Y |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| Hardware-assisted stack checking | Y | Y | TBD | N | | Hardware-assisted stack checking | Y | Y | TBD | N | N |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| Hardware-assisted atomic operations | N/A | Y | TBD | Y | | Hardware-assisted atomic operations | N/A | Y | TBD | Y | Y |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| DSP ISA | Y | N [#f3]_ | TBD | TBD | | DSP ISA | Y | N [#f3]_ | TBD | TBD | TBD |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| DSP AGU/XY extensions | N [#f3]_ | N [#f3]_ | TBD | TBD | | DSP AGU/XY extensions | N [#f3]_ | N [#f3]_ | TBD | TBD | TBD |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| Userspace | Y | Y | N | TBD | | Userspace | Y | Y | N | TBD | TBD |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| Memory protection unit (MPU) | Y | Y | TBD | N | | Memory protection unit (MPU) | Y | Y | TBD | N | N |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| Memory management unit (MMU) | N/A | N | N/A | N | | Memory management unit (MMU) | N/A | N | N/A | N | N |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| SecureShield | Y | N/A | N/A | N/A | | SecureShield | Y | N/A | N/A | N/A | N/A |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| **Toolchains** | | **Toolchains** |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| GNU (open source GCC-based) | Y | Y | N | Y | | GNU (open source GCC-based) | Y | Y | N | Y | Y |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| MetaWare (proprietary Clang-based) | Y | Y | Y | WIP [#f4]_ | | MetaWare (proprietary Clang-based) | Y | Y | Y | Y | Y |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| **Simulators** | | **Simulators** |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| QEMU (open source) [#f5]_ | Y | Y | N | Y | | QEMU (open source) [#f4]_ | Y | Y | N | Y | Y |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
| nSIM (proprietary, provided by MetaWare Development Tools) | Y | Y | Y | Y | | nSIM (proprietary, provided by MetaWare Development Tools) | Y | Y | Y | Y | Y |
+---------------------------------------------------------------------+------------+-------------+--------+------------+ +---------------------------------------------------------------------+------------+-------------+--------+------------+------------+
Notes Notes
***** *****
@ -82,7 +82,5 @@ Notes
Rest of DSP/AGU registers save/restore isn't implemented but kernel Rest of DSP/AGU registers save/restore isn't implemented but kernel
itself does not use these registers. This allows single task per itself does not use these registers. This allows single task per
core to use DSP/AGU safely. core to use DSP/AGU safely.
.. [#f4] MetaWare toolchain supports building for ARCv3 HS6x, however, it's .. [#f4] QEMU doesn't support all the ARC processor's HW features. For the
not integrated to Zephyr itself
.. [#f5] QEMU doesn't support all the ARC processor's HW features. For the
detailed info please check the ARC QEMU documentation detailed info please check the ARC QEMU documentation