soc: nuvoton: npcx: refactor npcx soc hierarchy for future chip support
This commit refactors the NPCX SoC hierarchy to improve maintainability and enable future support for upcoming chips. Key changes include: 1. Introduced a new `npcxn` subdirectory under `common/` to consolidate shared components across the npcxn series. 2. Renamed and reorganized register access files for improved consistency. 3. Updated relevant Kconfig files, header files, and CMakeLists for the new structure. Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
This commit is contained in:
Alvis Sun
Benjamin Cabé
parent
f10e7b8395
commit
dd578065bc
15 changed files with 786 additions and 789 deletions
|
|
@ -9,4 +9,17 @@ config SOC_FAMILY_NPCX
|
|||
config SOC_FAMILY
|
||||
default "nuvoton_npcx" if SOC_FAMILY_NPCX
|
||||
|
||||
config NPCX_SOC_VARIANT_NPCXN
|
||||
bool
|
||||
select SOC_FAMILY_NPCX
|
||||
|
||||
config NPCX_SOC_VARIANT_NPCKN
|
||||
bool
|
||||
select SOC_FAMILY_NPCX
|
||||
|
||||
config NPCX_SOC_VARIANT
|
||||
string
|
||||
default "npcxn" if NPCX_SOC_VARIANT_NPCXN
|
||||
default "npckn" if NPCX_SOC_VARIANT_NPCKN
|
||||
|
||||
rsource "*/Kconfig.soc"
|
||||
|
|
|
|||
|
|
@ -1,11 +1,13 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_sources_ifdef(CONFIG_PM power.c)
|
||||
zephyr_sources(
|
||||
scfg.c
|
||||
registers.c
|
||||
${CONFIG_NPCX_SOC_VARIANT}/registers.c
|
||||
)
|
||||
zephyr_include_directories(${CONFIG_NPCX_SOC_VARIANT}/include)
|
||||
|
||||
# Check for disabling header CRC.
|
||||
if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_HEADER_CRC)
|
||||
|
|
|
|||
113
soc/nuvoton/npcx/common/npcxn/include/clock_def.h
Normal file
113
soc/nuvoton/npcx/common/npcxn/include/clock_def.h
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_CLOCK_DEF_H_
|
||||
#define _NUVOTON_NPCX_CLOCK_DEF_H_
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <soc_clock.h>
|
||||
|
||||
/* FMUL clock */
|
||||
#if (OFMCLK > (MAX_OFMCLK / 2))
|
||||
#define FMCLK (OFMCLK / 2) /* FMUL clock = OFMCLK/2 */
|
||||
#else
|
||||
#define FMCLK OFMCLK /* FMUL clock = OFMCLK */
|
||||
#endif
|
||||
|
||||
/* APBs source clock */
|
||||
#define APBSRC_CLK OFMCLK
|
||||
|
||||
/* AHB6 clock */
|
||||
#if (CORE_CLK > (MAX_OFMCLK / 2))
|
||||
#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 */
|
||||
#else
|
||||
#define AHB6DIV_VAL 0 /* AHB6_CLK = CORE_CLK */
|
||||
#endif
|
||||
|
||||
/* FIU clock divider */
|
||||
#if (CORE_CLK > (MAX_OFMCLK / 2))
|
||||
#define FIUDIV_VAL 1 /* FIU_CLK = CORE_CLK/2 */
|
||||
#else
|
||||
#define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1)
|
||||
#if (CORE_CLK > (MAX_OFMCLK / 2))
|
||||
#define FIU1DIV_VAL 1 /* FIU1_CLK = CORE_CLK/2 */
|
||||
#else
|
||||
#define FIU1DIV_VAL 0 /* FIU1_CLK = CORE_CLK */
|
||||
#endif
|
||||
#endif /* CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1 */
|
||||
|
||||
/* I3C clock divider */
|
||||
#if (OFMCLK == MHZ(120)) /* MCLkD must between 40 mhz to 50 mhz*/
|
||||
#define MCLKD_SL 2 /* I3C_CLK = (MCLK / 3) */
|
||||
#elif (OFMCLK <= MHZ(100) && OFMCLK >= MHZ(80))
|
||||
#define MCLKD_SL 1 /* I3C_CLK = (MCLK / 2) */
|
||||
#else
|
||||
#define MCLKD_SL 0 /* I3C_CLK = MCLK */
|
||||
#endif
|
||||
|
||||
/* Get APB clock freq */
|
||||
#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
|
||||
|
||||
/*
|
||||
* Frequency multiplier M/N value definitions according to the requested
|
||||
* OFMCLK (Unit:Hz).
|
||||
*/
|
||||
#if (OFMCLK > (MAX_OFMCLK / 2))
|
||||
#define HFCGN_VAL 0x82 /* Set XF_RANGE as 1 */
|
||||
#else
|
||||
#define HFCGN_VAL 0x02
|
||||
#endif
|
||||
#if (OFMCLK == 120000000)
|
||||
#define HFCGMH_VAL 0x0E
|
||||
#define HFCGML_VAL 0x4E
|
||||
#elif (OFMCLK == 100000000)
|
||||
#define HFCGMH_VAL 0x0B
|
||||
#define HFCGML_VAL 0xEC
|
||||
#elif (OFMCLK == 96000000)
|
||||
#define HFCGMH_VAL 0x0B
|
||||
#define HFCGML_VAL 0x72
|
||||
#elif (OFMCLK == 90000000)
|
||||
#define HFCGMH_VAL 0x0A
|
||||
#define HFCGML_VAL 0xBA
|
||||
#elif (OFMCLK == 80000000)
|
||||
#define HFCGMH_VAL 0x09
|
||||
#define HFCGML_VAL 0x89
|
||||
#elif (OFMCLK == 66000000)
|
||||
#define HFCGMH_VAL 0x07
|
||||
#define HFCGML_VAL 0xDE
|
||||
#elif (OFMCLK == 50000000)
|
||||
#define HFCGMH_VAL 0x0B
|
||||
#define HFCGML_VAL 0xEC
|
||||
#elif (OFMCLK == 48000000)
|
||||
#define HFCGMH_VAL 0x0B
|
||||
#define HFCGML_VAL 0x72
|
||||
#else
|
||||
#error "Unsupported OFMCLK Frequency"
|
||||
#endif
|
||||
|
||||
/* Clock prescaler configurations in different series */
|
||||
#define VAL_HFCGP ((FPRED_VAL << 4) | AHB6DIV_VAL)
|
||||
#if defined(FIU1DIV_VAL)
|
||||
#define VAL_HFCBCD ((FIU1DIV_VAL << 4) | (FIUDIV_VAL << 2))
|
||||
#else
|
||||
#define VAL_HFCBCD (FIUDIV_VAL << 4)
|
||||
#endif /* FIU1DIV_VAL */
|
||||
#define VAL_HFCBCD1 (APB1DIV_VAL | (APB2DIV_VAL << 4))
|
||||
#if defined(APB4DIV_VAL)
|
||||
#define VAL_HFCBCD2 (APB3DIV_VAL | (APB4DIV_VAL << 4))
|
||||
#else
|
||||
#define VAL_HFCBCD2 APB3DIV_VAL
|
||||
#endif /* APB4DIV_VAL */
|
||||
/* I3C1~I3C3 share the same configuration */
|
||||
#define VAL_HFCBCD3 MCLKD_SL
|
||||
|
||||
#endif /* _NUVOTON_NPCX_CLOCK_DEF_H_ */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
* Copyright (c) 2025 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -7,49 +7,8 @@
|
|||
#ifndef _NUVOTON_NPCX_REG_DEF_H
|
||||
#define _NUVOTON_NPCX_REG_DEF_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <reg_access.h>
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/sys/__assert.h>
|
||||
#include <zephyr/sys/util_macro.h>
|
||||
#include <zephyr/toolchain.h>
|
||||
|
||||
/*
|
||||
* NPCX register structure size/offset checking macro function to mitigate
|
||||
* the risk of unexpected compiling results. All addresses of NPCX registers
|
||||
* must meet the alignment requirement of cortex-m4.
|
||||
* DO NOT use 'packed' attribute if module contains different length ie.
|
||||
* 8/16/32 bits registers.
|
||||
*/
|
||||
#define NPCX_REG_SIZE_CHECK(reg_def, size) \
|
||||
BUILD_ASSERT(sizeof(struct reg_def) == size, \
|
||||
"Failed in size check of register structure!")
|
||||
#define NPCX_REG_OFFSET_CHECK(reg_def, member, offset) \
|
||||
BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
|
||||
"Failed in offset check of register structure member!")
|
||||
|
||||
/*
|
||||
* NPCX register access checking via structure macro function to mitigate the
|
||||
* risk of unexpected compiling results if module contains different length
|
||||
* registers. For example, a word register access might break into two byte
|
||||
* register accesses by adding 'packed' attribute.
|
||||
*
|
||||
* For example, add this macro for word register 'PRSC' of PWM module in its
|
||||
* device init function for checking violation. Once it occurred, core will be
|
||||
* stalled forever and easy to find out what happens.
|
||||
*/
|
||||
#define NPCX_REG_WORD_ACCESS_CHECK(reg, val) { \
|
||||
uint16_t placeholder = reg; \
|
||||
reg = val; \
|
||||
__ASSERT(reg == val, "16-bit reg access failed!"); \
|
||||
reg = placeholder; \
|
||||
}
|
||||
#define NPCX_REG_DWORD_ACCESS_CHECK(reg, val) { \
|
||||
uint32_t placeholder = reg; \
|
||||
reg = val; \
|
||||
__ASSERT(reg == val, "32-bit reg access failed!"); \
|
||||
reg = placeholder; \
|
||||
}
|
||||
/*
|
||||
* Core Domain Clock Generator (CDCG) device registers
|
||||
*/
|
||||
|
|
@ -145,8 +104,7 @@ static inline uint32_t npcx_pwdwn_ctl_offset(uint32_t ctl_no)
|
|||
}
|
||||
|
||||
/* Macro functions for PMC multi-registers */
|
||||
#define NPCX_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + \
|
||||
npcx_pwdwn_ctl_offset(n)))
|
||||
#define NPCX_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + npcx_pwdwn_ctl_offset(n)))
|
||||
|
||||
/* PMC register fields */
|
||||
#define NPCX_PMCSR_DI_INSTW 0
|
||||
|
|
@ -235,16 +193,11 @@ struct scfg_reg {
|
|||
};
|
||||
|
||||
/* Macro functions for SCFG multi-registers */
|
||||
#define NPCX_DEV_CTL(base, n) \
|
||||
(*(volatile uint8_t *)(base + n))
|
||||
#define NPCX_DEVALT(base, n) \
|
||||
(*(volatile uint8_t *)(base + NPCX_DEVALT_OFFSET(n)))
|
||||
#define NPCX_DEVALT_LK(base, n) \
|
||||
(*(volatile uint8_t *)(base + NPCX_DEVALT_LK_OFFSET(n)))
|
||||
#define NPCX_PUPD_EN(base, n) \
|
||||
(*(volatile uint8_t *)(base + NPCX_PUPD_EN_OFFSET(n)))
|
||||
#define NPCX_LV_GPIO_CTL(base, n) \
|
||||
(*(volatile uint8_t *)(base + NPCX_LV_GPIO_CTL_OFFSET(n)))
|
||||
#define NPCX_DEV_CTL(base, n) (*(volatile uint8_t *)(base + n))
|
||||
#define NPCX_DEVALT(base, n) (*(volatile uint8_t *)(base + NPCX_DEVALT_OFFSET(n)))
|
||||
#define NPCX_DEVALT_LK(base, n) (*(volatile uint8_t *)(base + NPCX_DEVALT_LK_OFFSET(n)))
|
||||
#define NPCX_PUPD_EN(base, n) (*(volatile uint8_t *)(base + NPCX_PUPD_EN_OFFSET(n)))
|
||||
#define NPCX_LV_GPIO_CTL(base, n) (*(volatile uint8_t *)(base + NPCX_LV_GPIO_CTL_OFFSET(n)))
|
||||
|
||||
#define NPCX_JEN_CTL1_OFFSET 0x120
|
||||
#define NPCX_JEN_CTL1(base) (*(volatile uint8_t *)(base + (NPCX_JEN_CTL1_OFFSET)))
|
||||
|
|
@ -418,22 +371,14 @@ struct uart_reg {
|
|||
#define NPCX_UFRCTL_ERR_EN 7
|
||||
|
||||
/* Macro functions for MIWU multi-registers */
|
||||
#define NPCX_WKEDG(base, group) \
|
||||
(*(volatile uint8_t *)(base + NPCX_WKEDG_OFFSET(group)))
|
||||
#define NPCX_WKAEDG(base, group) \
|
||||
(*(volatile uint8_t *)(base + NPCX_WKAEDG_OFFSET(group)))
|
||||
#define NPCX_WKPND(base, group) \
|
||||
(*(volatile uint8_t *)(base + NPCX_WKPND_OFFSET(group)))
|
||||
#define NPCX_WKPCL(base, group) \
|
||||
(*(volatile uint8_t *)(base + NPCX_WKPCL_OFFSET(group)))
|
||||
#define NPCX_WKEN(base, group) \
|
||||
(*(volatile uint8_t *)(base + NPCX_WKEN_OFFSET(group)))
|
||||
#define NPCX_WKINEN(base, group) \
|
||||
(*(volatile uint8_t *)(base + NPCX_WKINEN_OFFSET(group)))
|
||||
#define NPCX_WKMOD(base, group) \
|
||||
(*(volatile uint8_t *)(base + NPCX_WKMOD_OFFSET(group)))
|
||||
#define NPCX_WKST(base, group) \
|
||||
(*(volatile uint8_t *)(base + NPCX_WKST_OFFSET(group)))
|
||||
#define NPCX_WKEDG(base, group) (*(volatile uint8_t *)(base + NPCX_WKEDG_OFFSET(group)))
|
||||
#define NPCX_WKAEDG(base, group) (*(volatile uint8_t *)(base + NPCX_WKAEDG_OFFSET(group)))
|
||||
#define NPCX_WKPND(base, group) (*(volatile uint8_t *)(base + NPCX_WKPND_OFFSET(group)))
|
||||
#define NPCX_WKPCL(base, group) (*(volatile uint8_t *)(base + NPCX_WKPCL_OFFSET(group)))
|
||||
#define NPCX_WKEN(base, group) (*(volatile uint8_t *)(base + NPCX_WKEN_OFFSET(group)))
|
||||
#define NPCX_WKINEN(base, group) (*(volatile uint8_t *)(base + NPCX_WKINEN_OFFSET(group)))
|
||||
#define NPCX_WKMOD(base, group) (*(volatile uint8_t *)(base + NPCX_WKMOD_OFFSET(group)))
|
||||
#define NPCX_WKST(base, group) (*(volatile uint8_t *)(base + NPCX_WKST_OFFSET(group)))
|
||||
|
||||
/*
|
||||
* General-Purpose I/O (GPIO) device registers
|
||||
|
|
@ -514,10 +459,8 @@ struct adc_reg {
|
|||
};
|
||||
|
||||
/* ADC internal inline functions for multi-registers */
|
||||
#define CHNDAT(base, ch) \
|
||||
(*(volatile uint16_t *)((base) + NPCX_CHNDAT_OFFSET(ch)))
|
||||
#define THRCTL(base, ctrl) \
|
||||
(*(volatile uint16_t *)(base + NPCX_THRCTL_OFFSET(ctrl)))
|
||||
#define CHNDAT(base, ch) (*(volatile uint16_t *)((base) + NPCX_CHNDAT_OFFSET(ch)))
|
||||
#define THRCTL(base, ctrl) (*(volatile uint16_t *)(base + NPCX_THRCTL_OFFSET(ctrl)))
|
||||
|
||||
/* ADC register fields */
|
||||
#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
|
||||
|
|
@ -1451,9 +1394,7 @@ struct ps2_reg {
|
|||
#define NPCX_PSOSIG_CLK(n) (((n) < 3) ? ((n) + 3) : 7)
|
||||
#define NPCX_PSOSIG_WDAT(n) (((n) < 3) ? ((n) + 0) : 6)
|
||||
#define NPCX_PSOSIG_CLK_MASK_ALL \
|
||||
(BIT(NPCX_PSOSIG_CLK0) | \
|
||||
BIT(NPCX_PSOSIG_CLK1) | \
|
||||
BIT(NPCX_PSOSIG_CLK2) | \
|
||||
(BIT(NPCX_PSOSIG_CLK0) | BIT(NPCX_PSOSIG_CLK1) | BIT(NPCX_PSOSIG_CLK2) | \
|
||||
BIT(NPCX_PSOSIG_CLK3))
|
||||
|
||||
#define NPCX_PSIEN_SOTIE 0
|
||||
|
|
@ -1573,22 +1514,16 @@ struct fiu_reg {
|
|||
|
||||
/* UMA code for transaction */
|
||||
#define UMA_CODE_CMD_ONLY (UMA_FLD_EXEC | UMA_FLD_SHD_SL)
|
||||
#define UMA_CODE_CMD_ADR (UMA_FLD_EXEC | UMA_FLD_ADDR | \
|
||||
UMA_FLD_SHD_SL)
|
||||
#define UMA_CODE_CMD_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FIELD_DATA_##n | \
|
||||
UMA_FLD_SHD_SL)
|
||||
#define UMA_CODE_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_NO_CMD | \
|
||||
UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
|
||||
#define UMA_CODE_CMD_WR_ONLY (UMA_FLD_EXEC | UMA_FLD_WRITE | \
|
||||
UMA_FLD_SHD_SL)
|
||||
#define UMA_CODE_CMD_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
|
||||
UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
|
||||
#define UMA_CODE_CMD_WR_ADR (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_ADDR | \
|
||||
UMA_FLD_SHD_SL)
|
||||
#define UMA_CODE_CMD_ADR (UMA_FLD_EXEC | UMA_FLD_ADDR | UMA_FLD_SHD_SL)
|
||||
#define UMA_CODE_CMD_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
|
||||
#define UMA_CODE_RD_BYTE(n) \
|
||||
(UMA_FLD_EXEC | UMA_FLD_NO_CMD | UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
|
||||
#define UMA_CODE_CMD_WR_ONLY (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_SHD_SL)
|
||||
#define UMA_CODE_CMD_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
|
||||
#define UMA_CODE_CMD_WR_ADR (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_ADDR | UMA_FLD_SHD_SL)
|
||||
|
||||
#define UMA_CODE_CMD_ADR_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
|
||||
UMA_FLD_ADDR | UMA_FIELD_DATA_##n | \
|
||||
UMA_FLD_SHD_SL)
|
||||
#define UMA_CODE_CMD_ADR_WR_BYTE(n) \
|
||||
(UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_ADDR | UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
|
||||
|
||||
/* Platform Environment Control Interface (PECI) device registers */
|
||||
struct peci_reg {
|
||||
|
|
@ -6,6 +6,7 @@
|
|||
|
||||
#include <zephyr/device.h>
|
||||
#include <soc.h>
|
||||
#include "reg_def.h"
|
||||
|
||||
/* CDCG register structure check */
|
||||
NPCX_REG_SIZE_CHECK(cdcg_reg, 0x116);
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_REG_ACCESS_H
|
||||
#define _NUVOTON_NPCX_REG_ACCESS_H
|
||||
|
||||
/*
|
||||
* NPCX register bit/field access operations
|
||||
*/
|
||||
|
||||
#define GET_POS_FIELD(pos, size) pos
|
||||
#define GET_SIZE_FIELD(pos, size) size
|
||||
#define FIELD_POS(field) GET_POS_##field
|
||||
#define FIELD_SIZE(field) GET_SIZE_##field
|
||||
|
||||
#define GET_FIELD(reg, field) \
|
||||
_GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
|
||||
#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1))
|
||||
|
||||
#define SET_FIELD(reg, field, value) \
|
||||
_SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
|
||||
#define _SET_FIELD_(reg, f_pos, f_size, value) \
|
||||
((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \
|
||||
| ((value) << (f_pos)))
|
||||
|
||||
#define GET_FIELD_POS(field) \
|
||||
_GET_FIELD_POS_(FIELD_POS(field))
|
||||
#define _GET_FIELD_POS_(f_ops) f_ops
|
||||
|
||||
#define GET_FIELD_SZ(field) \
|
||||
_GET_FIELD_SZ_(FIELD_SIZE(field))
|
||||
#define _GET_FIELD_SZ_(f_ops) f_ops
|
||||
|
||||
#endif /* _NUVOTON_NPCX_REG_ACCESS_H */
|
||||
71
soc/nuvoton/npcx/common/reg_access.h
Normal file
71
soc/nuvoton/npcx/common/reg_access.h
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _NUVOTON_NPCX_REG_ACCESS_H
|
||||
#define _NUVOTON_NPCX_REG_ACCESS_H
|
||||
|
||||
/*
|
||||
* NPCX register structure size/offset checking macro function to mitigate
|
||||
* the risk of unexpected compiling results. All addresses of NPCX registers
|
||||
* must meet the alignment requirement of cortex-m4.
|
||||
* DO NOT use 'packed' attribute if module contains different length ie.
|
||||
* 8/16/32 bits registers.
|
||||
*/
|
||||
#define NPCX_REG_SIZE_CHECK(reg_def, size) \
|
||||
BUILD_ASSERT(sizeof(struct reg_def) == size, "Failed in size check of register " \
|
||||
"structure!")
|
||||
#define NPCX_REG_OFFSET_CHECK(reg_def, member, offset) \
|
||||
BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
|
||||
"Failed in offset check of register structure member!")
|
||||
|
||||
/*
|
||||
* NPCX register access checking via structure macro function to mitigate the
|
||||
* risk of unexpected compiling results if module contains different length
|
||||
* registers. For example, a word register access might break into two byte
|
||||
* register accesses by adding 'packed' attribute.
|
||||
*
|
||||
* For example, add this macro for word register 'PRSC' of PWM module in its
|
||||
* device init function for checking violation. Once it occurred, core will be
|
||||
* stalled forever and easy to find out what happens.
|
||||
*/
|
||||
#define NPCX_REG_WORD_ACCESS_CHECK(reg, val) \
|
||||
{ \
|
||||
uint16_t placeholder = reg; \
|
||||
reg = val; \
|
||||
__ASSERT(reg == val, "16-bit reg access failed!"); \
|
||||
reg = placeholder; \
|
||||
}
|
||||
#define NPCX_REG_DWORD_ACCESS_CHECK(reg, val) \
|
||||
{ \
|
||||
uint32_t placeholder = reg; \
|
||||
reg = val; \
|
||||
__ASSERT(reg == val, "32-bit reg access failed!"); \
|
||||
reg = placeholder; \
|
||||
}
|
||||
|
||||
/*
|
||||
* NPCX register bit/field access operations
|
||||
*/
|
||||
|
||||
#define GET_POS_FIELD(pos, size) pos
|
||||
#define GET_SIZE_FIELD(pos, size) size
|
||||
#define FIELD_POS(field) GET_POS_##field
|
||||
#define FIELD_SIZE(field) GET_SIZE_##field
|
||||
|
||||
#define GET_FIELD(reg, field) _GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
|
||||
#define _GET_FIELD_(reg, f_pos, f_size) (((reg) >> (f_pos)) & ((1 << (f_size)) - 1))
|
||||
|
||||
#define SET_FIELD(reg, field, value) _SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
|
||||
#define _SET_FIELD_(reg, f_pos, f_size, value) \
|
||||
((reg) = ((reg) & (~(((1 << (f_size)) - 1) << (f_pos)))) | ((value) << (f_pos)))
|
||||
|
||||
#define GET_FIELD_POS(field) _GET_FIELD_POS_(FIELD_POS(field))
|
||||
#define _GET_FIELD_POS_(f_ops) f_ops
|
||||
|
||||
#define GET_FIELD_SZ(field) _GET_FIELD_SZ_(FIELD_SIZE(field))
|
||||
#define _GET_FIELD_SZ_(f_ops) f_ops
|
||||
|
||||
#endif /* _NUVOTON_NPCX_REG_ACCESS_H */
|
||||
|
|
@ -26,9 +26,9 @@ extern "C" {
|
|||
* register/bit to turn on/off its source clock.
|
||||
*/
|
||||
struct npcx_clk_cfg {
|
||||
uint16_t bus:8;
|
||||
uint16_t ctrl:5;
|
||||
uint16_t bit:3;
|
||||
uint16_t bus: 8;
|
||||
uint16_t ctrl: 5;
|
||||
uint16_t bit: 3;
|
||||
};
|
||||
|
||||
/* Clock settings from pcc node */
|
||||
|
|
@ -53,8 +53,8 @@ struct npcx_clk_cfg {
|
|||
|
||||
/* Construct a uint8_t array from 'pwdwn-ctl-val' prop for PWDWN_CTL initialization. */
|
||||
#define NPCX_PWDWN_CTL_ITEMS_INIT(node, prop, idx) DT_PROP_BY_IDX(node, prop, idx),
|
||||
#define NPCX_PWDWN_CTL_INIT DT_FOREACH_PROP_ELEM(DT_NODELABEL(pcc), \
|
||||
pwdwn_ctl_val, NPCX_PWDWN_CTL_ITEMS_INIT)
|
||||
#define NPCX_PWDWN_CTL_INIT \
|
||||
DT_FOREACH_PROP_ELEM(DT_NODELABEL(pcc), pwdwn_ctl_val, NPCX_PWDWN_CTL_ITEMS_INIT)
|
||||
|
||||
/*
|
||||
* NPCX7 and later series clock tree macros:
|
||||
|
|
@ -73,104 +73,6 @@ struct npcx_clk_cfg {
|
|||
/* Low Frequency clock */
|
||||
#define LFCLK 32768
|
||||
|
||||
/* FMUL clock */
|
||||
#if (OFMCLK > (MAX_OFMCLK / 2))
|
||||
#define FMCLK (OFMCLK / 2) /* FMUL clock = OFMCLK/2 */
|
||||
#else
|
||||
#define FMCLK OFMCLK /* FMUL clock = OFMCLK */
|
||||
#endif
|
||||
|
||||
/* APBs source clock */
|
||||
#define APBSRC_CLK OFMCLK
|
||||
|
||||
/* AHB6 clock */
|
||||
#if (CORE_CLK > (MAX_OFMCLK / 2))
|
||||
#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 */
|
||||
#else
|
||||
#define AHB6DIV_VAL 0 /* AHB6_CLK = CORE_CLK */
|
||||
#endif
|
||||
|
||||
/* FIU clock divider */
|
||||
#if (CORE_CLK > (MAX_OFMCLK / 2))
|
||||
#define FIUDIV_VAL 1 /* FIU_CLK = CORE_CLK/2 */
|
||||
#else
|
||||
#define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1)
|
||||
#if (CORE_CLK > (MAX_OFMCLK / 2))
|
||||
#define FIU1DIV_VAL 1 /* FIU1_CLK = CORE_CLK/2 */
|
||||
#else
|
||||
#define FIU1DIV_VAL 0 /* FIU1_CLK = CORE_CLK */
|
||||
#endif
|
||||
#endif /* CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1 */
|
||||
|
||||
/* I3C clock divider */
|
||||
#if (OFMCLK == MHZ(120)) /* MCLkD must between 40 mhz to 50 mhz*/
|
||||
#define MCLKD_SL 2 /* I3C_CLK = (MCLK / 3) */
|
||||
#elif (OFMCLK <= MHZ(100) && OFMCLK >= MHZ(80))
|
||||
#define MCLKD_SL 1 /* I3C_CLK = (MCLK / 2) */
|
||||
#else
|
||||
#define MCLKD_SL 0 /* I3C_CLK = MCLK */
|
||||
#endif
|
||||
|
||||
|
||||
/* Get APB clock freq */
|
||||
#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
|
||||
|
||||
/*
|
||||
* Frequency multiplier M/N value definitions according to the requested
|
||||
* OFMCLK (Unit:Hz).
|
||||
*/
|
||||
#if (OFMCLK > (MAX_OFMCLK / 2))
|
||||
#define HFCGN_VAL 0x82 /* Set XF_RANGE as 1 */
|
||||
#else
|
||||
#define HFCGN_VAL 0x02
|
||||
#endif
|
||||
#if (OFMCLK == 120000000)
|
||||
#define HFCGMH_VAL 0x0E
|
||||
#define HFCGML_VAL 0x4E
|
||||
#elif (OFMCLK == 100000000)
|
||||
#define HFCGMH_VAL 0x0B
|
||||
#define HFCGML_VAL 0xEC
|
||||
#elif (OFMCLK == 96000000)
|
||||
#define HFCGMH_VAL 0x0B
|
||||
#define HFCGML_VAL 0x72
|
||||
#elif (OFMCLK == 90000000)
|
||||
#define HFCGMH_VAL 0x0A
|
||||
#define HFCGML_VAL 0xBA
|
||||
#elif (OFMCLK == 80000000)
|
||||
#define HFCGMH_VAL 0x09
|
||||
#define HFCGML_VAL 0x89
|
||||
#elif (OFMCLK == 66000000)
|
||||
#define HFCGMH_VAL 0x07
|
||||
#define HFCGML_VAL 0xDE
|
||||
#elif (OFMCLK == 50000000)
|
||||
#define HFCGMH_VAL 0x0B
|
||||
#define HFCGML_VAL 0xEC
|
||||
#elif (OFMCLK == 48000000)
|
||||
#define HFCGMH_VAL 0x0B
|
||||
#define HFCGML_VAL 0x72
|
||||
#else
|
||||
#error "Unsupported OFMCLK Frequency"
|
||||
#endif
|
||||
|
||||
/* Clock prescaler configurations in different series */
|
||||
#define VAL_HFCGP ((FPRED_VAL << 4) | AHB6DIV_VAL)
|
||||
#if defined(FIU1DIV_VAL)
|
||||
#define VAL_HFCBCD ((FIU1DIV_VAL << 4) | (FIUDIV_VAL << 2))
|
||||
#else
|
||||
#define VAL_HFCBCD (FIUDIV_VAL << 4)
|
||||
#endif /* FIU1DIV_VAL */
|
||||
#define VAL_HFCBCD1 (APB1DIV_VAL | (APB2DIV_VAL << 4))
|
||||
#if defined(APB4DIV_VAL)
|
||||
#define VAL_HFCBCD2 (APB3DIV_VAL | (APB4DIV_VAL << 4))
|
||||
#else
|
||||
#define VAL_HFCBCD2 APB3DIV_VAL
|
||||
#endif /* APB4DIV_VAL */
|
||||
/* I3C1~I3C3 share the same configuration */
|
||||
#define VAL_HFCBCD3 MCLKD_SL
|
||||
|
||||
/**
|
||||
* @brief Function to notify clock driver that backup the counter value of
|
||||
* low-frequency timer before ec entered deep idle state.
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "reg/reg_def.h"
|
||||
#include "reg_def.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
|
||||
config SOC_SERIES_NPCX4
|
||||
bool
|
||||
select SOC_FAMILY_NPCX
|
||||
select NPCX_SOC_VARIANT_NPCXN
|
||||
help
|
||||
Enable support for Nuvoton NPCX4 series
|
||||
|
||||
|
|
|
|||
|
|
@ -50,10 +50,9 @@
|
|||
/* NPCX4 Clock Configuration */
|
||||
#define MAX_OFMCLK 120000000
|
||||
|
||||
#include <reg/reg_access.h>
|
||||
#include <reg/reg_def.h>
|
||||
#include "reg_def.h"
|
||||
#include "clock_def.h"
|
||||
#include <soc_dt.h>
|
||||
#include <soc_clock.h>
|
||||
#include <soc_espi_taf.h>
|
||||
#include <soc_pins.h>
|
||||
#include <soc_power.h>
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
|
||||
config SOC_SERIES_NPCX7
|
||||
bool
|
||||
select SOC_FAMILY_NPCX
|
||||
select NPCX_SOC_VARIANT_NPCXN
|
||||
help
|
||||
Enable support for Nuvoton NPCX7 series
|
||||
|
||||
|
|
|
|||
|
|
@ -42,10 +42,9 @@
|
|||
/* NPCX7 Clock configuration */
|
||||
#define MAX_OFMCLK 100000000
|
||||
|
||||
#include <reg/reg_access.h>
|
||||
#include <reg/reg_def.h>
|
||||
#include "reg_def.h"
|
||||
#include "clock_def.h"
|
||||
#include <soc_dt.h>
|
||||
#include <soc_clock.h>
|
||||
#include <soc_pins.h>
|
||||
#include <soc_power.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
|
||||
config SOC_SERIES_NPCX9
|
||||
bool
|
||||
select SOC_FAMILY_NPCX
|
||||
select NPCX_SOC_VARIANT_NPCXN
|
||||
help
|
||||
Enable support for Nuvoton NPCX9 series
|
||||
|
||||
|
|
|
|||
|
|
@ -47,10 +47,9 @@
|
|||
/* NPCX9 Clock configuration and limitation */
|
||||
#define MAX_OFMCLK 100000000
|
||||
|
||||
#include <reg/reg_access.h>
|
||||
#include <reg/reg_def.h>
|
||||
#include "reg_def.h"
|
||||
#include "clock_def.h"
|
||||
#include <soc_dt.h>
|
||||
#include <soc_clock.h>
|
||||
#include <soc_pins.h>
|
||||
#include <soc_power.h>
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue