soc: nxp mcxc: Add support for NXP MCXC series

Add initial suport for NXP MCXC series

Signed-off-by: Michal Smola <michal.smola@nxp.com>

soc/nxp/mcx/mcxc/CMakeLists.txt

@@ -0,0 +1,21 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources_ifdef(CONFIG_MCXC_FLASH_CONFIG	flash_configuration.c)
+
+zephyr_include_directories(.)
+
+zephyr_sources(soc.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
+
+zephyr_linker_sources_ifdef(CONFIG_MCXC_FLASH_CONFIG
+  ROM_START
+  SORT_KEY ${CONFIG_MCXC_FLASH_CONFIG_OFFSET}
+  flash_config.ld
+  )
+
+# CMSIS SystemInit will disable watchdog unless instructed not to.
+# Add a compiler definition here to leave watchdog untouched
+# if this Kconfig is set
+zephyr_compile_definitions_ifdef(CONFIG_WDOG_ENABLE_AT_BOOT DISABLE_WDOG=0)

soc/nxp/mcx/mcxc/Kconfig

@@ -0,0 +1,52 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_MCXC
+	select ARM
+	select CPU_CORTEX_M0PLUS
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
+	select CLOCK_CONTROL
+	select PLATFORM_SPECIFIC_INIT
+	select HAS_MCUX
+	select HAS_MCUX_ADC16
+	select HAS_MCUX_SIM
+	select HAS_MCUX_RCM
+	select HAS_MCUX_FTFX
+	select HAS_MCUX_LPUART
+	select HAS_MCUX_LPI2C
+	select HAS_MCUX_TPM
+
+if SOC_SERIES_MCXC
+
+config MCXC_FLASH_CONFIG
+	bool "MCXC flash configuration field"
+	default y if XIP && !BOOTLOADER_MCUBOOT
+	help
+	  Include the 16-byte flash configuration field that stores default
+	  protection settings (loaded on reset) and security information that
+	  allows the MCU to restrict access to the FTFx module.
+
+if MCXC_FLASH_CONFIG
+
+config MCXC_FLASH_CONFIG_OFFSET
+	hex
+	default $(dt_node_int_prop_hex,/soc/flash-controller@40020000,config-field-offset)
+
+endif # MCXC_FLASH_CONFIG
+
+config WDOG_ENABLE_AT_BOOT
+	bool "Keep watchdog timer enabled at boot"
+	help
+	  Leave SOC watchdog timer enabled at boot. The specific timeout
+	  and clock configuration of the watchdog at boot is SOC dependent.
+	  Note: if the watchdog timer is enabled at boot, the user will
+	  need to configure the watchdog using z_arm_watchdog_init, as
+	  the SOC requires watchdog configuration before initial expiration
+
+# Enable watchdog configuration function if watchdog is left enabled at boot
+config WDOG_INIT
+	bool
+	default WDOG_ENABLE_AT_BOOT
+
+endif # SOC_FAMILY_MCXC

soc/nxp/mcx/mcxc/Kconfig.defconfig

@@ -0,0 +1,12 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_MCXC
+
+config NUM_IRQS
+	default 32
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 48000000
+
+endif # SOC_SERIES_MCXC

soc/nxp/mcx/mcxc/Kconfig.soc

@@ -0,0 +1,48 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_MCXC
+	bool
+	select SOC_FAMILY_NXP_MCX
+
+config SOC_SERIES
+	default "mcxc" if SOC_SERIES_MCXC
+
+config SOC_MCXC141
+	bool
+	select SOC_SERIES_MCXC
+
+config SOC_MCXC142
+	bool
+	select SOC_SERIES_MCXC
+
+config SOC_MCXC242
+	bool
+	select SOC_SERIES_MCXC
+
+config SOC
+	default "mcxc141" if SOC_MCXC141
+	default "mcxc142" if SOC_MCXC142
+	default "mcxc242" if SOC_MCXC242
+
+config SOC_PART_NUMBER_MCXC141VLH
+	bool
+
+config SOC_PART_NUMBER_MCXC141VFM
+	bool
+
+config SOC_PART_NUMBER_MCXC142VFM
+	bool
+
+config SOC_PART_NUMBER_MCXC242VLH
+	bool
+
+config SOC_PART_NUMBER_MCXC242VFM
+	bool
+
+config SOC_PART_NUMBER
+	default "MCXC141VFM" if SOC_PART_NUMBER_MCXC141VLH
+	default "MCXC141VFM" if SOC_PART_NUMBER_MCXC141VFM
+	default "MCXC141VFM" if SOC_PART_NUMBER_MCXC142VFM
+	default "MCXC242VLH" if SOC_PART_NUMBER_MCXC242VLH
+	default "MCXC242VFM" if SOC_PART_NUMBER_MCXC242VFM

soc/nxp/mcx/mcxc/flash_config.ld

@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ #include <zephyr/devicetree.h>
+
+
+. = DT_PROP(DT_NODELABEL(ftfa), config_field_offset);
+KEEP(*(.kinetis_flash_config))
+KEEP(*(".kinetis_flash_config.*"))

soc/nxp/mcx/mcxc/flash_configuration.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/linker/sections.h>
+#include <zephyr/device.h>
+
+uint8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
+	/* Backdoor Comparison Key (unused) */
+	0xFF,
+	0xFF,
+	0xFF,
+	0xFF,
+	0xFF,
+	0xFF,
+	0xFF,
+	0xFF,
+
+	/* Program flash protection; 1 bit/region - 0=protected, 1=unprotected
+	 */
+	0xFF,
+	0xFF,
+	0xFF,
+	0xFF,
+
+	/* Flash security register (FSEC) enables/disables backdoor key access,
+	 * mass erase, factory access, and flash security
+	 */
+	DT_PROP_OR(DT_NODELABEL(ftfa), fsec, 0xFF),
+
+	/* Flash nonvolatile option register (FOPT) enables/disables NMI,
+	 * EzPort, and boot options
+	 */
+	DT_PROP_OR(DT_NODELABEL(ftfa), fopt, 0xFF),
+
+	/* EEPROM protection register (FEPROT) for FlexNVM devices */
+	0xFF,
+
+	/* Data flash protection register (FDPROT) for FlexNVM devices */
+	0XFF,
+};

soc/nxp/mcx/mcxc/pinctrl_soc.h

@@ -0,0 +1,49 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_ARM_NXP_MCXC_COMMON_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_ARM_NXP_MCXC_COMMON_PINCTRL_SOC_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef uint32_t pinctrl_soc_pin_t;
+
+/* MCXC series does not support open drain. Define macros to have no effect */
+#define PORT_PCR_ODE(x) 0x0
+#define PORT_PCR_ODE_MASK 0x0
+
+#define Z_PINCTRL_MCXC_PINCFG(node_id)					\
+	(PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) |			\
+	PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) |				\
+	PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) |				\
+	PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) |				\
+	PORT_PCR_ODE(DT_PROP(node_id, drive_open_drain)) |			\
+	PORT_PCR_SRE(DT_ENUM_IDX(node_id, slew_rate)) |				\
+	PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter)))
+
+#define Z_PINCTRL_KINETIS_PCR_MASK						\
+	(PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | PORT_PCR_ODE_MASK |		\
+	PORT_PCR_PFE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_PE_MASK |		\
+	PORT_PCR_PS_MASK)
+
+
+#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx)					\
+	DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_MCXC_PINCFG(group),
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)				\
+	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop),			\
+		DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_SOC_ARM_NXP_MCXC_COMMON_PINCTRL_SOC_H_ */

soc/nxp/mcx/mcxc/soc.c

@@ -0,0 +1,111 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <soc.h>
+#include <fsl_common.h>
+#include <fsl_clock.h>
+#include <zephyr/arch/cpu.h>
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define MCG_NODE DT_NODELABEL(mcg)
+#define OSC_NODE DT_NODELABEL(osc)
+
+#define SIM_LPUART_CLK_SEL_DISABLED     0U /*!< LPUART clock select: Disabled */
+#define SIM_LPUART_CLK_SEL_IRC48M_CLK   1U /*!< LPUART clock select: IRC48M clock */
+#define SIM_LPUART_CLK_SEL_OSCERCLK_CLK 2U /*!< LPUART clock select: OSCERCLK clock */
+#define SIM_LPUART_CLK_SEL_MCGIRCLK_CLK 3U /*!< LPUART clock select: MCGIRCLK clock */
+
+#define CLOCK_NODEID(clk) DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
+
+#define CLOCK_DIVIDER(clk) DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
+
+#define LPUART_CLOCK_SEL(label) \
+	(DT_PHA(DT_NODELABEL(label), clocks, name) == kCLOCK_McgIrc48MClk \
+		 ? SIM_LPUART_CLK_SEL_IRC48M_CLK \
+	 : DT_PHA(DT_NODELABEL(label), clocks, name) == kCLOCK_Osc0ErClk \
+		 ? SIM_LPUART_CLK_SEL_OSCERCLK_CLK \
+	 : DT_PHA(DT_NODELABEL(label), clocks, name) == kCLOCK_McgInternalRefClk \
+		 ? SIM_LPUART_CLK_SEL_MCGIRCLK_CLK \
+		 : SIM_LPUART_CLK_SEL_DISABLED)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = {
+	.outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
+	.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled */
+	.ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock */
+	/* Low-frequency Reference Clock Divider */
+	.fcrdiv = DT_PROP_OR(MCG_NODE, fcrdiv, 0),
+	/* Second Low-frequency Reference Clock Divider */
+	.lircDiv2 = DT_PROP_OR(MCG_NODE, lircdiv2, 0),
+	.hircEnableInNotHircMode = true, /* HIRC source is enabled */
+};
+
+const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
+	.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
+	.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
+		   SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
+};
+
+const osc_config_t oscConfig_BOARD_BootClockRUN = {
+	.freq = DT_PROP(OSC_NODE, clock_frequency),
+	.capLoad = 0,
+#if DT_ENUM_HAS_VALUE(OSC_NODE, mode, external)
+	.workMode = kOSC_ModeExt,
+#elif DT_ENUM_HAS_VALUE(OSC_NODE, mode, low_power)
+	.workMode = kOSC_ModeOscLowPower,
+#elif DT_ENUM_HAS_VALUE(OSC_NODE, mode, high_gain)
+	.workMode = kOSC_ModeOscHighGain,
+#else
+	#error "An oscillator mode must be defined"
+#endif
+	.oscerConfig = {
+		.enableMode = kOSC_ErClkEnable,
+	}
+};
+
+static void clock_init(void)
+{
+	/* Set the system clock dividers in SIM to safe value. */
+	CLOCK_SetSimSafeDivs();
+	/* Initializes OSC0 according to board configuration. */
+	CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
+	CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
+	/* Set MCG to HIRC mode. */
+	CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
+	/* Set the clock configuration in SIM module. */
+	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+	/* Set SystemCoreClock variable. */
+	SystemCoreClock = DT_PROP(DT_NODELABEL(cpu0), clock_frequency);
+	/* Set LPUART0 clock source. */
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart0), okay)
+	CLOCK_SetLpuart0Clock(LPUART_CLOCK_SEL(lpuart0));
+#endif
+}
+
+static int mcxc_init(void)
+{
+	clock_init();
+	return 0;
+}
+
+#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+
+void z_arm_platform_init(void)
+{
+	SystemInit();
+}
+
+#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+
+SYS_INIT(mcxc_init, PRE_KERNEL_1, 0);

soc/nxp/mcx/mcxc/soc.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#include <zephyr/sys/util.h>
+#include <fsl_port.h>
+
+#define UART0_CLK_SRC kCLOCK_CoreSysClk
+
+#define PORT_MUX_GPIO kPORT_MuxAsGpio /* GPIO setting for the Port Mux Register */
+
+#ifndef _ASMLANGUAGE
+
+#include <fsl_common.h>
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _SOC__H_ */

soc/nxp/mcx/soc.yml

@@ -8,6 +8,11 @@ family:
       - name: cpu0
       - name: cpu1
     - name: mcxn236
+  - name: mcxc
+    socs:
+    - name: mcxc141
+    - name: mcxc142
+    - name: mcxc242
 runners:
   run_once:
     '--erase':