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soc: nxp: imx8mm/n/p imx93/95: enable GIC safe config

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Enable CONFIG_GIC_SAFE_CONFIG by default for Cortex-A Core platforms
as the most targets are to run multiple OSes together with Zephyr on
different Cortex-A Cores.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
This commit is contained in:
Jiafei Pan 2024-12-30 12:03:11 +08:00 • committed by Benjamin Cabé
commit dd0446ae26
5 changed files with 20 additions and 0 deletions
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4
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_a53
View file

@ -12,6 +12,10 @@ config FLASH_SIZE
config FLASH_BASE_ADDRESS
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
# Enable GIC Safe Configuration to run multiple OSes on Cortex-A Cores
config GIC_SAFE_CONFIG
default y
config NUM_IRQS
default 240

4
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm6_a53
View file

@ -12,6 +12,10 @@ config FLASH_SIZE
config FLASH_BASE_ADDRESS
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
# Enable GIC Safe Configuration to run multiple OSes on Cortex-A Cores
config GIC_SAFE_CONFIG
default y
config NUM_IRQS
default 240

4
soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn6_a53
View file

@ -12,6 +12,10 @@ config FLASH_SIZE
config FLASH_BASE_ADDRESS
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
# Enable GIC Safe Configuration to run multiple OSes on Cortex-A Cores
config GIC_SAFE_CONFIG
default y
config NUM_IRQS
default 240

4
soc/nxp/imx/imx9/imx93/Kconfig.defconfig.mimx93.a55
View file

@ -12,6 +12,10 @@ config FLASH_SIZE
config FLASH_BASE_ADDRESS
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
# Enable GIC Safe Configuration to run multiple OSes on Cortex-A Cores
config GIC_SAFE_CONFIG
default y
config NUM_IRQS
default 240

4
soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.a55
View file

@ -12,6 +12,10 @@ config FLASH_SIZE
config FLASH_BASE_ADDRESS
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
# Enable GIC Safe Configuration to run multiple OSes on Cortex-A Cores
config GIC_SAFE_CONFIG
default y
config NUM_IRQS
default 320