diff --git a/dts/bindings/cpu/renesas,rx.yaml b/dts/bindings/cpu/renesas,rx.yaml index f0da8e59001..3f19e4ad687 100644 --- a/dts/bindings/cpu/renesas,rx.yaml +++ b/dts/bindings/cpu/renesas,rx.yaml @@ -1,4 +1,5 @@ # Copyright (c) 2021 KT-Elektronik Klaucke und Partner GmbH +# Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 description: Renesas RX CPU diff --git a/dts/bindings/flash_controller/renesas,rx-flash.yaml b/dts/bindings/flash_controller/renesas,rx-flash.yaml new file mode 100644 index 00000000000..99e6d1a01cf --- /dev/null +++ b/dts/bindings/flash_controller/renesas,rx-flash.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RX Flash region + +compatible: "renesas,rx-flash" + +include: flash-controller.yaml diff --git a/dts/bindings/interrupt-controller/renesas,rx-icu.yaml b/dts/bindings/interrupt-controller/renesas,rx-icu.yaml new file mode 100644 index 00000000000..5816177fd3c --- /dev/null +++ b/dts/bindings/interrupt-controller/renesas,rx-icu.yaml @@ -0,0 +1,22 @@ +# Copyright (c) 2021 KT-Elektronik Klaucke und Partner GmbH +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas ICU Interrupt controller +compatible: "renesas,rx-icu" + +include: [interrupt-controller.yaml, base.yaml] + +properties: + reg: + required: true + + reg-names: + required: true + + "#interrupt-cells": + const: 2 + +interrupt-cells: + - irq + - priority diff --git a/dts/bindings/mtd/renesas,rx-nv-flash.yaml b/dts/bindings/mtd/renesas,rx-nv-flash.yaml new file mode 100644 index 00000000000..2dda49b3f96 --- /dev/null +++ b/dts/bindings/mtd/renesas,rx-nv-flash.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Flash memory binding of Renesas RX family + +include: [base.yaml, soc-nv-flash.yaml] + +compatible: "renesas,rx-nv-flash" diff --git a/dts/rx/renesas/r5f513083xfb.dtsi b/dts/rx/renesas/r5f513083xfb.dtsi new file mode 100644 index 00000000000..663be86ea4a --- /dev/null +++ b/dts/rx/renesas/r5f513083xfb.dtsi @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include + +/ { + clocks: clocks { + xtal: clock-xtal { + compatible = "renesas,rx-cgc-external-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "okay"; + }; + + loco: clock-loco { + compatible = "fixed-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "okay"; + }; + + subclk: clock-subclk { + compatible = "renesas,rx-cgc-subclk"; + clock-frequency = <32768>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,rx-cgc-pll"; + #clock-cells = <0>; + + /* PLL */ + source = ; + div = ; + mul = <8 0>; + }; + + pclkblock: pclkblock { + compatible = "renesas,rx-cgc-pclk-block"; + #clock-cells = <0>; + sysclock-src = ; + status = "okay"; + + iclk: iclk { + compatible = "renesas,rx-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,rx-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,rx-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,rx-cgc-pclk"; + clk_div = ; + #clock-cells = <2>; + status = "okay"; + }; + }; + }; + + soc { + sram0: memory@0 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x0 DT_SIZE_K(48)>; + }; + + fcu: flash-controller@7e0000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "renesas,rx-flash.yaml"; + reg = <0x007e0000 0x1000>; + + code_flash: flash@fff80000 { + compatible = "renesas,rx-nv-flash.yaml"; + reg = <0xfff80000 DT_SIZE_K(512)>; + write-block-size = <4>; + erase-block-size = <1024>; + }; + + data_flash: flash@100000 { + compatible = "renesas,rx-nv-flash.yaml"; + erased_undefined; + reg = <0x00100000 DT_SIZE_K(8)>; + write_block_size = <1>; + erase-block-size = <1024>; + }; + }; + }; +}; diff --git a/dts/rx/renesas/rx130-common.dtsi b/dts/rx/renesas/rx130-common.dtsi new file mode 100644 index 00000000000..2eef76b22a0 --- /dev/null +++ b/dts/rx/renesas/rx130-common.dtsi @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * common device tree elements of all (currently supported) RX MCUs + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "renesas,rx"; + device_type = "cpu"; + reg = <0>; + status = "okay"; + }; + }; + + icu: interrupt-controller@87000 { + #interrupt-cells = <2>; + compatible = "renesas,rx-icu"; + interrupt-controller; + reg = <0x0087000 0xff>, + <0x0087200 0x1f>, + <0x0087300 0xff>, + <0x00872f0 0x02>; + reg-names = "IR", "IER", "IPR", "FIR"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + interrupt-parent = <&icu>; + + pinctrl: pin-controller@8c11f { + compatible = "renesas,rx-pinctrl"; + reg = <0x0008C11F 0x3c0>; + status = "okay"; + }; + + ioport0: gpio@8c000 { + compatible = "renesas,rx-gpio"; + reg = <0x0008C000 0x20>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + status = "disabled"; + }; + + sci0: sci0@8a000 { + compatible = "renesas,rx-sci"; + reg = <0x0008A000 0x100>; + status = "disabled"; + + uart { + compatible = "renesas,rx-uart-sci"; + status = "disabled"; + }; + }; + + cmt0: timer@88004 { + compatible = "renesas,rx-timer-cmt"; + reg = <0x00088004 0x02>, + <0x00088000 0x02>, + <0x00088002 0x02>, + <0x00088006 0x02>; + status = "disabled"; + }; + + ofsm: ofsm@ffffff80 { + compatible = "zephyr,memory-region"; + reg = <0xFFFFFF80 0x0F>; + zephyr,memory-region = "OFSM"; + status = "okay"; + }; + }; +}; diff --git a/modules/Kconfig b/modules/Kconfig index 3b7f9dcb4ba..7d32d1ff818 100644 --- a/modules/Kconfig +++ b/modules/Kconfig @@ -33,7 +33,7 @@ source "modules/Kconfig.microchip" source "modules/Kconfig.nuvoton" source "modules/Kconfig.open-amp" source "modules/Kconfig.picolibc" -source "modules/Kconfig.renesas_fsp" +source "modules/Kconfig.renesas" source "modules/Kconfig.rust" source "modules/Kconfig.simplelink" source "modules/Kconfig.sof" diff --git a/modules/Kconfig.renesas_fsp b/modules/Kconfig.renesas similarity index 96% rename from modules/Kconfig.renesas_fsp rename to modules/Kconfig.renesas index 01fd54cb081..0adb757c814 100644 --- a/modules/Kconfig.renesas_fsp +++ b/modules/Kconfig.renesas @@ -241,3 +241,12 @@ config USE_RZ_FSP_SCI_UART Enable RZ FSP SCI UART driver endif + +config HAS_RENESAS_RX_RDP + bool + help + Enable Renesas RX RDP support + +if HAS_RENESAS_RX_RDP + +endif # HAS_RENESAS_RX_RDP diff --git a/soc/renesas/rx/CMakeLists.txt b/soc/renesas/rx/CMakeLists.txt new file mode 100644 index 00000000000..15633d88be6 --- /dev/null +++ b/soc/renesas/rx/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) +zephyr_include_directories(common) + +add_subdirectory(common) +add_subdirectory(${SOC_SERIES}) diff --git a/soc/renesas/rx/Kconfig b/soc/renesas/rx/Kconfig new file mode 100644 index 00000000000..f0670b850e3 --- /dev/null +++ b/soc/renesas/rx/Kconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_RENESAS_RX + select BUILD_OUTPUT_MOT + +if SOC_FAMILY_RENESAS_RX + +config RENESAS_NONE_USED_PORT_INIT + bool "Initialize unused ports" + default y + help + Initialize the unsed pins of RX MCU followed by in the "Handling of + Unused Pins" section of PORT chapter of RX MCU of User's manual. + Note: please MUST set "BSP_PACKAGE_PINS" definition to your device + of pin type in r_bsp_config.h. + Otherwise, the port may output without intention. + +rsource "*/Kconfig" + +endif # SOC_FAMILY_RENESAS_RX diff --git a/soc/renesas/rx/Kconfig.defconfig b/soc/renesas/rx/Kconfig.defconfig new file mode 100644 index 00000000000..bda0f2eaa62 --- /dev/null +++ b/soc/renesas/rx/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_RX + +rsource "*/Kconfig.defconfig" + +endif diff --git a/soc/renesas/rx/Kconfig.soc b/soc/renesas/rx/Kconfig.soc new file mode 100644 index 00000000000..f2174c1c4e9 --- /dev/null +++ b/soc/renesas/rx/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_RENESAS_RX + bool + +config SOC_FAMILY + default "renesas_rx" if SOC_FAMILY_RENESAS_RX + +rsource "*/Kconfig.soc" diff --git a/soc/renesas/rx/common/CMakeLists.txt b/soc/renesas/rx/common/CMakeLists.txt new file mode 100644 index 00000000000..a5a0f2c3236 --- /dev/null +++ b/soc/renesas/rx/common/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(reg_protection.c) diff --git a/soc/renesas/rx/common/reg_protection.c b/soc/renesas/rx/common/reg_protection.c new file mode 100644 index 00000000000..e69504b38ed --- /dev/null +++ b/soc/renesas/rx/common/reg_protection.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "reg_protection.h" +#if CONFIG_HAS_RENESAS_RX_RDP +#include "r_bsp_cpu.h" +#endif + +#define PRCR_KEY (0xA500) +#define SYSTEM_PRCR (*(volatile uint16_t *)0x000803FE) + +#ifndef CONFIG_HAS_RENESAS_RX_RDP +static volatile uint16_t protect_counters[RENESAS_RX_REG_PROTECT_TOTAL_ITEMS]; + +static const uint16_t prcr_masks[RENESAS_RX_REG_PROTECT_TOTAL_ITEMS] = { + 0x0001, /* PRC0. */ + 0x0002, /* PRC1. */ + 0x0004, /* PRC2. */ + 0x0008, /* PRC3. */ +}; + + +void renesas_rx_register_protect_open(void) +{ + int i; + + for (i = 0; i < RENESAS_RX_REG_PROTECT_TOTAL_ITEMS; i++) { + protect_counters[i] = 0; + } +} +#endif + +void renesas_rx_register_protect_enable(renesas_rx_reg_protect_t regs_to_protect) +{ +#if CONFIG_HAS_RENESAS_RX_RDP + R_BSP_RegisterProtectEnable(regs_to_protect); +#else + int key; + + /* + * Set IPL to the maximum value to disable all interrupts, + * so the scheduler can not be scheduled in critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. + */ + key = irq_lock(); + + /* Is it safe to disable write access? */ + if (0 != protect_counters[regs_to_protect]) { + /* Decrement the protect counter */ + protect_counters[regs_to_protect]--; + } + + /* Is it safe to disable write access? */ + if (0 == protect_counters[regs_to_protect]) { + /* + * Enable protection using PRCR register. + * When writing to the PRCR register the upper 8-bits must be the correct key. Set + * lower bits to 0 to disable writes. b15:b8 PRKEY - Write 0xA5 to upper byte to + * enable writing to lower byte b7:b4 Reserved (set to 0) b3 PRC3 - Please + * check the user's manual. b2 PRC2 - Please check the user's manual. b1 PRC1 + * - Please check the user's manual. b0 PRC0 - Please check the user's manual. + */ + SYSTEM_PRCR = (uint16_t)((SYSTEM_PRCR | PRCR_KEY) & (~prcr_masks[regs_to_protect])); + } + + /* Restore the IPL. */ + irq_unlock(key); +#endif +} + +void renesas_rx_register_protect_disable(renesas_rx_reg_protect_t regs_to_unprotect) +{ +#if CONFIG_HAS_RENESAS_RX_RDP + R_BSP_RegisterProtectDisable(regs_to_unprotect); +#else + int key; + + /* + * Set IPL to the maximum value to disable all interrupts, + * so the scheduler cannot be scheduled in the critical region. + * Note: Please set this macro more than IPR for other FIT module interrupts. + */ + key = irq_lock(); + + /* Is it safe to enable write access? */ + if (0 == protect_counters[regs_to_unprotect]) { + /* Disable protection using PRCR register */ + SYSTEM_PRCR = (uint16_t)((SYSTEM_PRCR | PRCR_KEY) | prcr_masks[regs_to_unprotect]); + } + + /* Increment the protect counter */ + protect_counters[regs_to_unprotect]++; + + /* Restore the IPL */ + irq_unlock(key); +#endif +} /* End of function renesas_register_protect_disable() */ diff --git a/soc/renesas/rx/common/reg_protection.h b/soc/renesas/rx/common/reg_protection.h new file mode 100644 index 00000000000..bfc2fcf837a --- /dev/null +++ b/soc/renesas/rx/common/reg_protection.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_SOC_RENESAS_REG_PROTECTION_H_ +#define ZEPHYR_INCLUDE_SOC_RENESAS_REG_PROTECTION_H_ + +typedef enum { + /* + * PRC0 + * Enables writing to the registers related to the clock generation circuit: SCKCR, SCKCR3, + * PLLCR, PLLCR2, MOSCCR, SOSCCR, LOCOCR, ILOCOCR, HOCOCR, HOFCR, OSTDCR, OSTDSR, CKOCR, + * LOCOTRR, ILOCOTRR, HOCOTRR0. + */ + RENESAS_RX_REG_PROTECT_CGC = 0, + + /* + * PRC1 + * Enables writing to the registers related to operating modes, low power consumption, + * the clock generation circuit, and software reset: SYSCR1, SBYCR, MSTPCRA, MSTPCRB, + * MSTPCRC, MSTPCRD, OPCCR, RSTCKCR, SOPCCR, MOFCR, MOSCWTCR, SWRR. + */ + RENESAS_RX_REG_PROTECT_LPC_CGC_SWR, + + /* + * PRC2 + * Enables writing to the registers related to the LPT: LPTCR1, LPTCR2, LPTCR3, LPTPRD, + * LPCMR0, LPWUCR. + */ + RENESAS_RX_REG_PROTECT_LPT, + + /* + * PRC3 + * Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, + * LVD1SR, LVD2CR0, LVD2CR1, LVD2SR. + */ + RENESAS_RX_REG_PROTECT_LVD, + + /* + * MPC.PWPR + * Enables writing to MPC's PFS registers. + */ + RENESAS_RX_REG_PROTECT_MPC, + + /* + * This entry is used for getting the number of enum items. This must be the last entry. DO + * NOT REMOVE THIS ENTRY! + */ + RENESAS_RX_REG_PROTECT_TOTAL_ITEMS +} renesas_rx_reg_protect_t; + +void renesas_rx_register_protect_open(void); +void renesas_rx_register_protect_enable(renesas_rx_reg_protect_t regs_to_protect); +void renesas_rx_register_protect_disable(renesas_rx_reg_protect_t regs_to_unprotect); + +#endif /* ZEPHYR_INCLUDE_SOC_RENESAS_REG_PROTECTION_H_ */ diff --git a/soc/renesas/rx/rx130/CMakeLists.txt b/soc/renesas/rx/rx130/CMakeLists.txt new file mode 100644 index 00000000000..7e162148e8d --- /dev/null +++ b/soc/renesas/rx/rx130/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c +) + +zephyr_linker_sources(SECTIONS ofsm.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/rx/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rx/rx130/Kconfig b/soc/renesas/rx/rx130/Kconfig new file mode 100644 index 00000000000..b68231bcd37 --- /dev/null +++ b/soc/renesas/rx/rx130/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RX130 + select RX + select CPU_RXV1 + select XIP diff --git a/soc/renesas/rx/rx130/Kconfig.defconfig b/soc/renesas/rx/rx130/Kconfig.defconfig new file mode 100644 index 00000000000..ecfc7a86e34 --- /dev/null +++ b/soc/renesas/rx/rx130/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RX130 + +config INITIALIZATION_STACK_SIZE + default 512 + +endif # SOC_SERIES_RX130 diff --git a/soc/renesas/rx/rx130/Kconfig.soc b/soc/renesas/rx/rx130/Kconfig.soc new file mode 100644 index 00000000000..417497a510c --- /dev/null +++ b/soc/renesas/rx/rx130/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RX130 + bool + select SOC_FAMILY_RENESAS_RX + help + Renesas RX130 series + +config SOC_R5F513083XFB + bool + select SOC_SERIES_RX130 + help + R5F513083XFB + +config SOC_SERIES + default "rx130" if SOC_SERIES_RX130 + +config SOC + default "r5f513083xfb" if SOC_R5F513083XFB diff --git a/soc/renesas/rx/rx130/ofsm.c b/soc/renesas/rx/rx130/ofsm.c new file mode 100644 index 00000000000..70fc502503e --- /dev/null +++ b/soc/renesas/rx/rx130/ofsm.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * + * Option-Setting Memory for the RX. This region of memory (located in flash) + * determines the state of the MCU after reset and can not be changed on runtime + * + * All registers are set to 0xffffffff by default, which are "safe" settings. + * Please refer to the Renesas RX Group User's Manual before changing any of + * the values as some changes can be permanent or lock access to the device. + * + * Address range: 0xFE7F5D00 to 0xFE7F5D7F (128 Bytes) + */ + +#define __OFS_MDE __attribute__((section(".ofs_mde"))) + +/* Endian Select Register (MDE) at 0xFE7F5D00 + * + * b2 to b0: endian select between (0 0 0) for big endian and (1 1 1) for little + * endian. Set this according to __BYTE_ORDER__ (cf. include\toolchain\gcc.h) + * + * b6-b4 (Bank Mode Select) indicate whether the flash is operated in + * Dual mode (0 0 0) or Linear mode (1 1 1). + * + * all other bits are reserved and have to be set to 1 + */ +const unsigned long __OFS_MDE __MDEreg = 0xffffffff; /* little */ + +struct st_ofs0 { + unsigned long res0: 1; + unsigned long IWDTSTRT: 1; + unsigned long IWDTTOPS: 2; + unsigned long IWDTCKS: 4; + unsigned long IWDTRPES: 2; + unsigned long IWDTRPSS: 2; + unsigned long IWDTRSTIRQS: 1; + unsigned long res1: 1; + unsigned long IWDTSLCSTP: 1; + unsigned long res2: 16; +}; + +const unsigned long __OFS_MDE __OFS0reg = 0xffffffff; + +/* Option Function Select Register 1 (OFS1) at 0xFE7F5D08 (Voltage detection and + * HOCO) + */ +const unsigned long __OFS_MDE __OFS1reg = 0xffffffff; diff --git a/soc/renesas/rx/rx130/ofsm.ld b/soc/renesas/rx/rx130/ofsm.ld new file mode 100644 index 00000000000..410277b5cbf --- /dev/null +++ b/soc/renesas/rx/rx130/ofsm.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +SECTION_PROLOGUE(.ofsm,,) +{ + __OFSM_START = .; + KEEP(*(.ofs_mde)) + . = __OFSM_START + 0x8; + KEEP(*(.ofs1)) + . = __OFSM_START + 0xC; + KEEP(*(.ofs0)) + __OFSM_END = .; +} GROUP_LINK_IN(OFSM) = 0xFF diff --git a/soc/renesas/rx/rx130/soc.c b/soc/renesas/rx/rx130/soc.c new file mode 100644 index 00000000000..3c9b2add564 --- /dev/null +++ b/soc/renesas/rx/rx130/soc.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief System/hardware module for RX SOC family + */ + +#include +#include +#include +#include +#include + +#include "platform.h" +#include "r_bsp_cpu.h" + +extern +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +void soc_early_init_hook(void) +{ +#ifdef CONFIG_HAS_RENESAS_RX_RDP + bsp_ram_initialize(); + bsp_interrupt_open(); + bsp_register_protect_open(); +#if CONFIG_RENESAS_NONE_USED_PORT_INIT == 1 + /* + * This is the function that initializes the unused port. + * Please see datails on this in the "Handling of Unused Pins" section of PORT chapter + * of RX MCU of User's manual. + * And please MUST set "BSP_PACKAGE_PINS" definition to your device of pin type in + * r_bsp_config.h Otherwise, the port may output without intention. + */ + bsp_non_existent_port_init(); + +#endif /* CONFIG_RENESAS_NONE_USED_PORT_INIT */ +#else + renesas_rx_register_protect_open(); +#endif /* CONFIG_HAS_RENESAS_RX_RDP */ +} diff --git a/soc/renesas/rx/rx130/soc.h b/soc/renesas/rx/rx130/soc.h new file mode 100644 index 00000000000..39aa634c09f --- /dev/null +++ b/soc/renesas/rx/rx130/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief SOC header file for Renesas RX SOC series + */ + +#ifndef _SOC_H_ +#define _SOC_H_ + +#include "reg_protection.h" + +#endif /* _SOC_H_ */ diff --git a/soc/renesas/rx/soc.yml b/soc/renesas/rx/soc.yml new file mode 100644 index 00000000000..594bb96db19 --- /dev/null +++ b/soc/renesas/rx/soc.yml @@ -0,0 +1,6 @@ +family: + - name: renesas_rx + series: + - name: rx130 + socs: + - name: r5f513083xfb