diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c index 265b7248d44..3369dbea39f 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019 Nordic Semiconductor ASA * Copyright (c) 2016 Vinayak Kariappa Chettimada * * SPDX-License-Identifier: Apache-2.0 @@ -116,6 +116,10 @@ void radio_reset(void) & RADIO_POWER_POWER_Msk); hal_radio_reset(); + +#if !defined(CONFIG_BT_CTLR_TIFS_HW) + hal_radio_sw_switch_ppi_group_setup(); +#endif } void radio_phy_set(u8_t phy, u8_t flags) @@ -286,10 +290,10 @@ void radio_tx_enable(void) void radio_disable(void) { #if !defined(CONFIG_BT_CTLR_TIFS_HW) - nrf_ppi_channels_disable(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) | + hal_radio_nrf_ppi_channels_disable(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) | BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI)); - nrf_ppi_group_disable(SW_SWITCH_TIMER_TASK_GROUP(0)); - nrf_ppi_group_disable(SW_SWITCH_TIMER_TASK_GROUP(1)); + hal_radio_nrf_ppi_group_disable(SW_SWITCH_TIMER_TASK_GROUP(0)); + hal_radio_nrf_ppi_group_disable(SW_SWITCH_TIMER_TASK_GROUP(1)); #endif /* !CONFIG_BT_CTLR_TIFS_HW */ NRF_RADIO->SHORTS = 0; @@ -388,12 +392,7 @@ static void sw_switch(u8_t dir, u8_t phy_curr, u8_t flags_curr, u8_t phy_next, u8_t cc = SW_SWITCH_TIMER_EVTS_COMP(sw_tifs_toggle); u32_t delay; - nrf_ppi_channel_endpoint_setup(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI, - HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_EVT, - HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_TASK(sw_tifs_toggle)); - - nrf_ppi_event_endpoint_setup(ppi, - HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(cc)); + hal_radio_sw_switch_setup(cc, ppi, sw_tifs_toggle); if (dir) { /* TX */ @@ -462,7 +461,7 @@ static void sw_switch(u8_t dir, u8_t phy_curr, u8_t flags_curr, u8_t phy_next, HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_TASK( sw_tifs_toggle); - nrf_ppi_channels_enable( + hal_radio_nrf_ppi_channels_enable( BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI)); } else { /* Switching to TX after RX on LE 1M/2M PHY */ @@ -535,7 +534,7 @@ static void sw_switch(u8_t dir, u8_t phy_curr, u8_t flags_curr, u8_t phy_next, nrf_timer_cc_write(SW_SWITCH_TIMER, cc, 1); } - nrf_ppi_channels_enable(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) | + hal_radio_nrf_ppi_channels_enable(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) | BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI)); #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER) @@ -583,8 +582,7 @@ void radio_switch_complete_and_disable(void) (RADIO_SHORTS_READY_START_Msk | RADIO_SHORTS_END_DISABLE_Msk); #if !defined(CONFIG_BT_CTLR_TIFS_HW) - nrf_ppi_channels_disable(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) | - BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI)); + hal_radio_sw_switch_disable(); #endif /* !CONFIG_BT_CTLR_TIFS_HW */ } @@ -667,7 +665,7 @@ void radio_tmr_status_reset(void) { nrf_rtc_event_disable(NRF_RTC0, RTC_EVTENCLR_COMPARE2_Msk); - nrf_ppi_channels_disable( + hal_radio_nrf_ppi_channels_disable( BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI) | BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI) | BIT(HAL_EVENT_TIMER_START_PPI) | @@ -715,7 +713,7 @@ u32_t radio_tmr_start(u8_t trx, u32_t ticks_start, u32_t remainder) nrf_rtc_event_enable(NRF_RTC0, RTC_EVTENSET_COMPARE2_Msk); hal_event_timer_start_ppi_config(); - nrf_ppi_channels_enable(BIT(HAL_EVENT_TIMER_START_PPI)); + hal_radio_nrf_ppi_channels_enable(BIT(HAL_EVENT_TIMER_START_PPI)); hal_radio_enable_on_tick_ppi_config_and_enable(trx); @@ -735,24 +733,9 @@ u32_t radio_tmr_start(u8_t trx, u32_t ticks_start, u32_t remainder) hal_sw_switch_timer_clear_ppi_config(); #if !defined(CONFIG_BT_CTLR_PHY_CODED) || !defined(CONFIG_SOC_NRF52840) - nrf_ppi_channel_endpoint_setup( - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(0), - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT( - SW_SWITCH_TIMER_EVTS_COMP(0)), - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK(0)); - nrf_ppi_channel_endpoint_setup( - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(1), - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT( - SW_SWITCH_TIMER_EVTS_COMP(1)), - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK(1)); + hal_radio_group_task_disable_ppi_setup(); - NRF_PPI->CHG[SW_SWITCH_TIMER_TASK_GROUP(0)] = - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_0_INCLUDE | - HAL_SW_SWITCH_RADIO_ENABLE_PPI_0_INCLUDE; - NRF_PPI->CHG[SW_SWITCH_TIMER_TASK_GROUP(1)] = - HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_1_INCLUDE | - HAL_SW_SWITCH_RADIO_ENABLE_PPI_1_INCLUDE; #else /* CONFIG_BT_CTLR_PHY_CODED && CONFIG_SOC_NRF52840 */ NRF_PPI->CHG[SW_SWITCH_TIMER_TASK_GROUP(0)] = HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_0_INCLUDE | @@ -783,7 +766,7 @@ u32_t radio_tmr_start_tick(u8_t trx, u32_t tick) nrf_rtc_event_enable(NRF_RTC0, RTC_EVTENSET_COMPARE2_Msk); hal_event_timer_start_ppi_config(); - nrf_ppi_channels_enable(BIT(HAL_EVENT_TIMER_START_PPI)); + hal_radio_nrf_ppi_channels_enable(BIT(HAL_EVENT_TIMER_START_PPI)); hal_radio_enable_on_tick_ppi_config_and_enable(trx); @@ -853,16 +836,18 @@ void radio_tmr_hcto_configure(u32_t hcto) hal_radio_recv_timeout_cancel_ppi_config(); hal_radio_disable_on_hcto_ppi_config(); - nrf_ppi_channels_enable(BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) | - BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI)); + hal_radio_nrf_ppi_channels_enable( + BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) | + BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI)); } void radio_tmr_aa_capture(void) { hal_radio_ready_time_capture_ppi_config(); hal_radio_recv_timeout_cancel_ppi_config(); - nrf_ppi_channels_enable(BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) | - BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI)); + hal_radio_nrf_ppi_channels_enable( + BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) | + BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI)); } u32_t radio_tmr_aa_get(void) @@ -891,7 +876,7 @@ u32_t radio_tmr_ready_get(void) void radio_tmr_end_capture(void) { hal_radio_end_time_capture_ppi_config(); - nrf_ppi_channels_enable(BIT(HAL_RADIO_END_TIME_CAPTURE_PPI)); + hal_radio_nrf_ppi_channels_enable(BIT(HAL_RADIO_END_TIME_CAPTURE_PPI)); } u32_t radio_tmr_end_get(void) @@ -1011,13 +996,13 @@ void radio_gpio_pa_lna_enable(u32_t trx_us) hal_enable_palna_ppi_config(); hal_disable_palna_ppi_config(); - nrf_ppi_channels_enable(BIT(HAL_ENABLE_PALNA_PPI) | + hal_radio_nrf_ppi_channels_enable(BIT(HAL_ENABLE_PALNA_PPI) | BIT(HAL_DISABLE_PALNA_PPI)); } void radio_gpio_pa_lna_disable(void) { - nrf_ppi_channels_disable(BIT(HAL_ENABLE_PALNA_PPI) | + hal_radio_nrf_ppi_channels_disable(BIT(HAL_ENABLE_PALNA_PPI) | BIT(HAL_DISABLE_PALNA_PPI)); } #endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */ @@ -1067,7 +1052,8 @@ void *radio_ccm_rx_pkt_set(struct ccm *ccm, u8_t phy, void *pkt) CCM_RATEOVERRIDE_RATEOVERRIDE_Msk; hal_trigger_rateoverride_ppi_config(); - nrf_ppi_channels_enable(BIT(HAL_TRIGGER_RATEOVERRIDE_PPI)); + hal_radio_nrf_ppi_channels_enable( + BIT(HAL_TRIGGER_RATEOVERRIDE_PPI)); break; #endif /* CONFIG_SOC_NRF52840 */ #endif /* CONFIG_BT_CTLR_PHY_CODED */ @@ -1084,7 +1070,7 @@ void *radio_ccm_rx_pkt_set(struct ccm *ccm, u8_t phy, void *pkt) NRF_CCM->EVENTS_ERROR = 0; hal_trigger_crypt_ppi_config(); - nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI)); + hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI)); nrf_ccm_task_trigger(NRF_CCM, NRF_CCM_TASK_KSGEN); @@ -1162,7 +1148,7 @@ void radio_ar_configure(u32_t nirk, void *irk) radio_bc_status_reset(); hal_trigger_aar_ppi_config(); - nrf_ppi_channels_enable(BIT(HAL_TRIGGER_AAR_PPI)); + hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_AAR_PPI)); } u32_t radio_ar_match_get(void) diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h index 6086200e946..84542dc7a3b 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019 Nordic Semiconductor ASA * Copyright (c) 2018 Ioannis Glaropoulos * * SPDX-License-Identifier: Apache-2.0 @@ -9,6 +9,21 @@ #include +static inline void hal_radio_nrf_ppi_channels_enable(u32_t mask) +{ + nrf_ppi_channels_enable(mask); +} + +static inline void hal_radio_nrf_ppi_channels_disable(u32_t mask) +{ + nrf_ppi_channels_disable(mask); +} + +static inline void hal_radio_nrf_ppi_group_disable(u32_t group) +{ + nrf_ppi_group_disable(group); +} + /******************************************************************************* * Enable Radio on Event Timer tick: * wire the EVENT_TIMER EVENTS_COMPARE[0] event to RADIO TASKS_TXEN/RXEN task. @@ -383,6 +398,29 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void) #define HAL_SW_SWITCH_RADIO_ENABLE_PPI_TASK_RX \ ((u32_t)&(NRF_RADIO->TASKS_RXEN)) +static inline void hal_radio_sw_switch_setup( + u8_t compare_reg, + u8_t radio_enable_ppi, + u8_t ppi_group_index) +{ + /* Set up software switch mechanism for next Radio switch. */ + + /* Wire RADIO END event to PPI Group[] enable task, + * over PPI[] + */ + nrf_ppi_channel_endpoint_setup(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI, + HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_EVT, + HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_TASK(ppi_group_index)); + + /* Wire SW Switch timer event to the + * PPI[] for enabling Radio. Do + * not wire the task; it is done by the caller of + * the function depending on the desired direction + * (TX/RX). + */ + nrf_ppi_event_endpoint_setup(radio_enable_ppi, + HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(compare_reg)); +} static inline void hal_radio_txen_on_sw_switch(u8_t ppi) { @@ -396,6 +434,16 @@ static inline void hal_radio_rxen_on_sw_switch(u8_t ppi) HAL_SW_SWITCH_RADIO_ENABLE_PPI_TASK_RX); } +static inline void hal_radio_sw_switch_disable(void) +{ + /* Disable the following PPI channels that implement SW Switch: + * - Clearing SW SWITCH TIMER on RADIO END event + * - Enabling SW SWITCH PPI Group on RADIO END event + */ + nrf_ppi_channels_disable(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) | + BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI)); +} + #if defined(CONFIG_SOC_NRF52840) /* The 2 adjacent TIMER EVENTS_COMPARE event offsets used for implementing * SW_SWITCH_TIMER-based auto-switch for TIFS, when receiving in LE Coded PHY. @@ -432,7 +480,41 @@ static inline void hal_radio_rxen_on_sw_switch(u8_t ppi) #define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_TASK(index) \ ((u32_t)&(SW_SWITCH_TIMER->TASKS_CAPTURE[index])) +#else + +static inline void hal_radio_group_task_disable_ppi_setup(void) +{ + /* Wire SW SWITCH TIMER EVENTS COMPARE event to + * PPI Group TASK [] DISABLE task, over PPI. + */ + nrf_ppi_channel_endpoint_setup( + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(0), + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT( + SW_SWITCH_TIMER_EVTS_COMP(0)), + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK(0)); + + /* Wire SW SWITCH TIMER event to + * PPI Group[] Disable Task, over PPI. + */ + nrf_ppi_channel_endpoint_setup( + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(1), + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT( + SW_SWITCH_TIMER_EVTS_COMP(1)), + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK(1)); +} #endif /* CONFIG_SOC_NRF52840 */ + +static inline void hal_radio_sw_switch_ppi_group_setup(void) +{ + /* Include the appropriate PPI channels in the two PPI Groups. */ + NRF_PPI->CHG[SW_SWITCH_TIMER_TASK_GROUP(0)] = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_0_INCLUDE | + HAL_SW_SWITCH_RADIO_ENABLE_PPI_0_INCLUDE; + NRF_PPI->CHG[SW_SWITCH_TIMER_TASK_GROUP(1)] = + HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_1_INCLUDE | + HAL_SW_SWITCH_RADIO_ENABLE_PPI_1_INCLUDE; +} + #endif /* !CONFIG_BT_CTLR_TIFS_HW */ /******************************************************************************/