net: mii: use BIT() macro in mii.h
use BIT() macro in mii.h. Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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Fin Maaß
Dan Kalowsky
parent
8ed5f0370e
commit
db79e78b98
1 changed files with 48 additions and 46 deletions
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@ -12,6 +12,8 @@
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#ifndef ZEPHYR_INCLUDE_NET_MII_H_
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#define ZEPHYR_INCLUDE_NET_MII_H_
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#include <zephyr/sys/util_macro.h>
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/**
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* @brief Ethernet MII (media independent interface) functions
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* @defgroup ethernet_mii Ethernet MII Support Functions
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@ -41,9 +43,9 @@
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/** Auto-Negotiation Link Partner Received Next Page Reg */
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#define MII_ANLPRNPR 0x8
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/** 1000BASE-T Control Register */
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#define MII_1KTCR 0x9
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#define MII_1KTCR 0x9
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/** 1000BASE-T Status Register */
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#define MII_1KSTSR 0xa
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#define MII_1KSTSR 0xa
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/** MMD Access Control Register */
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#define MII_MMD_ACR 0xd
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/** MMD Access Address Data Register */
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@ -53,86 +55,86 @@
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/* Basic Mode Control Register (BMCR) bit definitions */
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/** PHY reset */
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#define MII_BMCR_RESET (1 << 15)
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#define MII_BMCR_RESET BIT(15)
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/** enable loopback mode */
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#define MII_BMCR_LOOPBACK (1 << 14)
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#define MII_BMCR_LOOPBACK BIT(14)
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/** 10=1000Mbps 01=100Mbps; 00=10Mbps */
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#define MII_BMCR_SPEED_LSB (1 << 13)
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#define MII_BMCR_SPEED_LSB BIT(13)
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/** Auto-Negotiation enable */
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#define MII_BMCR_AUTONEG_ENABLE (1 << 12)
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#define MII_BMCR_AUTONEG_ENABLE BIT(12)
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/** power down mode */
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#define MII_BMCR_POWER_DOWN (1 << 11)
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#define MII_BMCR_POWER_DOWN BIT(11)
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/** isolate electrically PHY from MII */
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#define MII_BMCR_ISOLATE (1 << 10)
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#define MII_BMCR_ISOLATE BIT(10)
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/** restart auto-negotiation */
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#define MII_BMCR_AUTONEG_RESTART (1 << 9)
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#define MII_BMCR_AUTONEG_RESTART BIT(9)
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/** full duplex mode */
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#define MII_BMCR_DUPLEX_MODE (1 << 8)
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#define MII_BMCR_DUPLEX_MODE BIT(8)
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/** 10=1000Mbps 01=100Mbps; 00=10Mbps */
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#define MII_BMCR_SPEED_MSB (1 << 6)
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#define MII_BMCR_SPEED_MSB BIT(6)
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/** Link Speed Field */
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#define MII_BMCR_SPEED_MASK (1 << 6 | 1 << 13)
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#define MII_BMCR_SPEED_MASK (BIT(6) | BIT(13))
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/** select speed 10 Mb/s */
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#define MII_BMCR_SPEED_10 (0 << 6 | 0 << 13)
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#define MII_BMCR_SPEED_10 0
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/** select speed 100 Mb/s */
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#define MII_BMCR_SPEED_100 (0 << 6 | 1 << 13)
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#define MII_BMCR_SPEED_100 BIT(13)
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/** select speed 1000 Mb/s */
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#define MII_BMCR_SPEED_1000 (1 << 6 | 0 << 13)
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#define MII_BMCR_SPEED_1000 BIT(6)
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/* Basic Mode Status Register (BMSR) bit definitions */
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/** 100BASE-T4 capable */
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#define MII_BMSR_100BASE_T4 (1 << 15)
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#define MII_BMSR_100BASE_T4 BIT(15)
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/** 100BASE-X full duplex capable */
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#define MII_BMSR_100BASE_X_FULL (1 << 14)
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#define MII_BMSR_100BASE_X_FULL BIT(14)
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/** 100BASE-X half duplex capable */
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#define MII_BMSR_100BASE_X_HALF (1 << 13)
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#define MII_BMSR_100BASE_X_HALF BIT(13)
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/** 10 Mb/s full duplex capable */
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#define MII_BMSR_10_FULL (1 << 12)
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#define MII_BMSR_10_FULL BIT(12)
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/** 10 Mb/s half duplex capable */
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#define MII_BMSR_10_HALF (1 << 11)
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#define MII_BMSR_10_HALF BIT(11)
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/** 100BASE-T2 full duplex capable */
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#define MII_BMSR_100BASE_T2_FULL (1 << 10)
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#define MII_BMSR_100BASE_T2_FULL BIT(10)
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/** 100BASE-T2 half duplex capable */
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#define MII_BMSR_100BASE_T2_HALF (1 << 9)
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#define MII_BMSR_100BASE_T2_HALF BIT(9)
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/** extend status information in reg 15 */
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#define MII_BMSR_EXTEND_STATUS (1 << 8)
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#define MII_BMSR_EXTEND_STATUS BIT(8)
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/** PHY accepts management frames with preamble suppressed */
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#define MII_BMSR_MF_PREAMB_SUPPR (1 << 6)
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#define MII_BMSR_MF_PREAMB_SUPPR BIT(6)
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/** Auto-negotiation process completed */
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#define MII_BMSR_AUTONEG_COMPLETE (1 << 5)
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#define MII_BMSR_AUTONEG_COMPLETE BIT(5)
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/** remote fault detected */
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#define MII_BMSR_REMOTE_FAULT (1 << 4)
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#define MII_BMSR_REMOTE_FAULT BIT(4)
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/** PHY is able to perform Auto-Negotiation */
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#define MII_BMSR_AUTONEG_ABILITY (1 << 3)
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#define MII_BMSR_AUTONEG_ABILITY BIT(3)
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/** link is up */
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#define MII_BMSR_LINK_STATUS (1 << 2)
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#define MII_BMSR_LINK_STATUS BIT(2)
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/** jabber condition detected */
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#define MII_BMSR_JABBER_DETECT (1 << 1)
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#define MII_BMSR_JABBER_DETECT BIT(1)
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/** extended register capabilities */
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#define MII_BMSR_EXTEND_CAPAB (1 << 0)
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#define MII_BMSR_EXTEND_CAPAB BIT(0)
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/* Auto-negotiation Advertisement Register (ANAR) bit definitions */
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/* Auto-negotiation Link Partner Ability Register (ANLPAR) bit definitions */
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/** next page */
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#define MII_ADVERTISE_NEXT_PAGE (1 << 15)
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#define MII_ADVERTISE_NEXT_PAGE BIT(15)
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/** link partner acknowledge response */
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#define MII_ADVERTISE_LPACK (1 << 14)
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#define MII_ADVERTISE_LPACK BIT(14)
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/** remote fault */
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#define MII_ADVERTISE_REMOTE_FAULT (1 << 13)
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#define MII_ADVERTISE_REMOTE_FAULT BIT(13)
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/** try for asymmetric pause */
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#define MII_ADVERTISE_ASYM_PAUSE (1 << 11)
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#define MII_ADVERTISE_ASYM_PAUSE BIT(11)
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/** try for pause */
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#define MII_ADVERTISE_PAUSE (1 << 10)
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#define MII_ADVERTISE_PAUSE BIT(10)
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/** try for 100BASE-T4 support */
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#define MII_ADVERTISE_100BASE_T4 (1 << 9)
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#define MII_ADVERTISE_100BASE_T4 BIT(9)
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/** try for 100BASE-X full duplex support */
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#define MII_ADVERTISE_100_FULL (1 << 8)
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#define MII_ADVERTISE_100_FULL BIT(8)
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/** try for 100BASE-X support */
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#define MII_ADVERTISE_100_HALF (1 << 7)
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#define MII_ADVERTISE_100_HALF BIT(7)
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/** try for 10 Mb/s full duplex support */
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#define MII_ADVERTISE_10_FULL (1 << 6)
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#define MII_ADVERTISE_10_FULL BIT(6)
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/** try for 10 Mb/s half duplex support */
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#define MII_ADVERTISE_10_HALF (1 << 5)
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#define MII_ADVERTISE_10_HALF BIT(5)
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/** Selector Field Mask */
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#define MII_ADVERTISE_SEL_MASK (0x1F << 0)
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/** Selector Field */
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@ -140,9 +142,9 @@
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/* 1000BASE-T Control Register bit definitions */
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/** try for 1000BASE-T full duplex support */
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#define MII_ADVERTISE_1000_FULL (1 << 9)
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#define MII_ADVERTISE_1000_FULL BIT(9)
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/** try for 1000BASE-T half duplex support */
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#define MII_ADVERTISE_1000_HALF (1 << 8)
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#define MII_ADVERTISE_1000_HALF BIT(8)
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/** Advertise all speeds */
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#define MII_ADVERTISE_ALL (MII_ADVERTISE_10_HALF | MII_ADVERTISE_10_FULL |\
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@ -151,13 +153,13 @@
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/* Extended Status Register bit definitions */
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/** 1000BASE-X full-duplex capable */
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#define MII_ESTAT_1000BASE_X_FULL (1 << 15)
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#define MII_ESTAT_1000BASE_X_FULL BIT(15)
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/** 1000BASE-X half-duplex capable */
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#define MII_ESTAT_1000BASE_X_HALF (1 << 14)
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#define MII_ESTAT_1000BASE_X_HALF BIT(14)
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/** 1000BASE-T full-duplex capable */
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#define MII_ESTAT_1000BASE_T_FULL (1 << 13)
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#define MII_ESTAT_1000BASE_T_FULL BIT(13)
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/** 1000BASE-T half-duplex capable */
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#define MII_ESTAT_1000BASE_T_HALF (1 << 12)
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#define MII_ESTAT_1000BASE_T_HALF BIT(12)
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/* MMD Access Control Register (MII_MMD_ACR) Register bit definitions */
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/** DEVAD Mask */
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