From db3cd1a833d99062c37ec40f0893ce59f415a09b Mon Sep 17 00:00:00 2001 From: Karsten Koenig Date: Fri, 11 Apr 2025 12:20:46 +0200 Subject: [PATCH] drivers: cache: Add barriers to nrf driver On Cortex-M33 the access to peripheral registers doesn't act as a data synchronization barrier for memory accesses to normal memory. So before triggering any TASKS for cache operations we need to make sure the core doesn't have any pending memory transactions. Signed-off-by: Karsten Koenig --- drivers/cache/cache_nrf.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/cache/cache_nrf.c b/drivers/cache/cache_nrf.c index 3cf79897874..90f13581ba9 100644 --- a/drivers/cache/cache_nrf.c +++ b/drivers/cache/cache_nrf.c @@ -5,6 +5,7 @@ */ #include #include +#include #include #include @@ -67,6 +68,8 @@ static inline int _cache_all(NRF_CACHE_Type *cache, enum k_nrf_cache_op op) wait_for_cache(cache); + barrier_dsync_fence_full(); + switch (op) { #if NRF_CACHE_HAS_TASK_CLEAN @@ -101,6 +104,8 @@ static inline void _cache_line(NRF_CACHE_Type *cache, enum k_nrf_cache_op op, ui nrf_cache_lineaddr_set(cache, line_addr); + barrier_dsync_fence_full(); + switch (op) { #if NRF_CACHE_HAS_TASK_CLEAN