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samples: drivers: fpga: fpga_controller: fix links in README.rst

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Markdown links were incorrectly used in this ReST document.

Signed-off-by: Chris Friedt <cfriedt@meta.com>
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Chris Friedt 2022-11-12 07:08:51 -05:00 • committed by Christopher Friedt
commit dae6d2f84b
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samples/drivers/fpga/fpga_controller/README.rst
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@ -7,7 +7,7 @@ Overview
********
This module is an FPGA driver that can easily load a bitstream, reset it, check its status, enable or disable the FPGA.
This sample demonstrates how to use the FPGA driver API and the the FPGA controller shell subsystem.
Currently the sample works with [Quicklogic Quickfeather board](https://github.com/QuickLogic-Corp/quick-feather-dev-board).
Currently the sample works with `Quicklogic Quickfeather board`_.
Requirements
************
@ -15,7 +15,7 @@ Requirements
* Zephyr RTOS
or
* Zephyr RTOS with shell subsystem enabled (for shell application)
* [Quicklogic Quickfeather board](https://github.com/QuickLogic-Corp/quick-feather-dev-board)
* `Quicklogic Quickfeather board`_
Building
********
@ -44,7 +44,7 @@ configuration file prj_shell.conf:
Running
*******
See [QuickFeather programming and debugging](https://docs.zephyrproject.org/latest/boards/arm/quick_feather/doc/index.html#programming-and-debugging) on how to load an image to the board.
See :ref:`quickfeather` on how to load an image to the board.
Sample output
=============
@ -113,3 +113,9 @@ Now the bitstream can be uploaded again.
uart:~$ fpga load FPGA 0x10000 75960
FPGA: loading bitstream
References
**********
.. _Quicklogic Quickfeather board:
https://github.com/QuickLogic-Corp/quick-feather-dev-board