style: soc: comply with MISRA C:2012 Rule 15.6

Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>

soc/aspeed/ast10x0/soc.c

@@ -107,10 +107,11 @@ void aspeed_print_abr_wdt_mode(void)
 	/* ABR enable */
 	if (sys_read32(HW_STRAP2_SCU510) & BIT(11)) {
 		printk("FMC ABR: Enable");
-		if (sys_read32(HW_STRAP2_SCU510) & BIT(12))
+		if (sys_read32(HW_STRAP2_SCU510) & BIT(12)) {
 			printk(", Single flash");
-		else
+		} else {
 			printk(", Dual flashes");
+		}
 
 		printk(", Source: %s (%d)",
 			(sys_read32(ASPEED_FMC_WDT2_CTRL) & BIT(4)) ? "Alternate" : "Primary",

soc/intel/intel_adsp/ace/comm_widget_messages.c

@@ -16,8 +16,9 @@
  */
 int adsp_comm_widget_pmc_send_ipc(uint16_t banks)
 {
-	if (!cw_upstream_ready())
+	if (!cw_upstream_ready()) {
 		return -EBUSY;
+	}
 
 	uint32_t iface = FIELD_PREP(CW_PMC_IPC_OP_CODE, CW_PMC_OPC_SRAM_CONFIG) |
 			 FIELD_PREP(CW_PMC_IPC_SRAM_USED_BANKS, banks) |

soc/intel/intel_adsp/common/include/soc_util.h

@@ -15,8 +15,9 @@ static ALWAYS_INLINE void bmemcpy(void *dest, void *src, size_t bytes)
 	volatile uint32_t *s = (uint32_t *)src;
 
 	sys_cache_data_invd_range(src, bytes);
-	for (size_t i = 0; i < (bytes >> 2); i++)
+	for (size_t i = 0; i < (bytes >> 2); i++) {
 		d[i] = s[i];
+	}
 
 	sys_cache_data_flush_range(dest, bytes);
 }
@@ -26,8 +27,9 @@ static ALWAYS_INLINE void bbzero(void *dest, size_t bytes)
 {
 	volatile uint32_t *d = (uint32_t *)dest;
 
-	for (size_t i = 0; i < (bytes >> 2); i++)
+	for (size_t i = 0; i < (bytes >> 2); i++) {
 		d[i] = 0;
+	}
 
 	sys_cache_data_flush_range(dest, bytes);
 }

soc/nxp/imx/imx6sx/soc.c

@@ -159,8 +159,9 @@ static void SOC_CacheInit(void)
 	LMEM_PSCCR = LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK;
 	LMEM_PSCCR |= LMEM_PSCCR_GO_MASK;
 	/* Wait until the command completes */
-	while (LMEM_PSCCR & LMEM_PSCCR_GO_MASK)
+	while (LMEM_PSCCR & LMEM_PSCCR_GO_MASK) {
 		;
+	}
 	/* Enable system bus cache, enable write buffer */
 	LMEM_PSCCR = (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
 	barrier_isync_fence_full();
@@ -172,8 +173,9 @@ static void SOC_CacheInit(void)
 	LMEM_PCCCR = LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
 	LMEM_PCCCR |= LMEM_PCCCR_GO_MASK;
 	/* Wait until the command completes */
-	while (LMEM_PCCCR & LMEM_PCCCR_GO_MASK)
+	while (LMEM_PCCCR & LMEM_PCCCR_GO_MASK) {
 		;
+	}
 	/* Enable code bus cache, enable write buffer */
 	LMEM_PCCCR = (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
 	barrier_isync_fence_full();

soc/nxp/imx/imx8/adsp/_soc_inthandlers.h

@@ -104,12 +104,13 @@ static inline int _xtensa_handle_one_int2(unsigned int mask)
 	int i = 0;
 
 	mask &= XCHAL_INTLEVEL2_MASK;
-	for (i = 0; i <= 31; i++)
+	for (i = 0; i <= 31; i++) {
 		if (mask & BIT(i)) {
 			mask = BIT(i);
 			irq = i;
 			goto handle_irq;
 		}
+	}
 	return 0;
 handle_irq:
 	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);

soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h

@@ -104,12 +104,13 @@ static inline int _xtensa_handle_one_int2(unsigned int mask)
 	int i = 0;
 
 	mask &= XCHAL_INTLEVEL2_MASK;
-	for (i = 0; i <= 31; i++)
+	for (i = 0; i <= 31; i++) {
 		if (mask & BIT(i)) {
 			mask = BIT(i);
 			irq = i;
 			goto handle_irq;
 		}
+	}
 	return 0;
 handle_irq:
 	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);

soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h

@@ -104,12 +104,13 @@ static inline int _xtensa_handle_one_int2(unsigned int mask)
 	int i = 0;
 
 	mask &= XCHAL_INTLEVEL2_MASK;
-	for (i = 0; i <= 31; i++)
+	for (i = 0; i <= 31; i++) {
 		if (mask & BIT(i)) {
 			mask = BIT(i);
 			irq = i;
 			goto handle_irq;
 		}
+	}
 	return 0;
 handle_irq:
 	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);

soc/sifive/sifive_freedom/fu500/clock.c

@@ -28,8 +28,9 @@ static int fu540_clock_init(void)
 		PLL_RANGE(PLL_RANGE_33MHZ) |
 		PLL_BYPASS(PLL_BYPASS_DISABLE) |
 		PLL_FSE(PLL_FSE_INTERNAL);
-	while ((PRCI_REG(PRCI_COREPLLCFG0) & PLL_LOCK(1)) == 0)
+	while ((PRCI_REG(PRCI_COREPLLCFG0) & PLL_LOCK(1)) == 0) {
 		;
+	}
 
 	/* Switch clock to COREPLL */
 	PRCI_REG(PRCI_CORECLKSEL) = CORECLKSEL_CORECLKSEL(CORECLKSEL_CORE_PLL);

soc/sifive/sifive_freedom/fu700/clock.c

@@ -40,8 +40,9 @@ static int fu740_clock_init(void)
 		PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */
 		PLL_BYPASS(PLL_BYPASS_DISABLE) |
 		PLL_FSE(PLL_FSE_INTERNAL);
-	while ((PRCI_REG(PRCI_COREPLLCFG) & PLL_LOCK(1)) == 0)
+	while ((PRCI_REG(PRCI_COREPLLCFG) & PLL_LOCK(1)) == 0) {
 		;
+	}
 
 	/* Switch CORE_CLK to CORE_PLL from HFCLK */
 	PRCI_REG(PRCI_COREPLLSEL) = COREPLLSEL_SEL(COREPLLSEL_COREPLL);
@@ -54,8 +55,9 @@ static int fu740_clock_init(void)
 		PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */
 		PLL_BYPASS(PLL_BYPASS_DISABLE) |
 		PLL_FSE(PLL_FSE_INTERNAL);
-	while ((PRCI_REG(PRCI_HFPCLKPLLCFG) & PLL_LOCK(1)) == 0)
+	while ((PRCI_REG(PRCI_HFPCLKPLLCFG) & PLL_LOCK(1)) == 0) {
 		;
+	}
 
 	/* Switch PCLK to HFPCLKPLL/2 from HFCLK/2 */
 	PRCI_REG(PRCI_HFPCLKPLLOUTDIV) = OUTDIV_PLLCKE(OUTDIV_PLLCKE_ENA);
@@ -68,8 +70,9 @@ static int fu740_clock_init(void)
 		PLL_RANGE(PLL_RANGE_18MHZ) |
 		PLL_BYPASS(PLL_BYPASS_DISABLE) |
 		PLL_FSE(PLL_FSE_INTERNAL);
-	while ((PRCI_REG(PRCI_DDRPLLCFG) & PLL_LOCK(1)) == 0)
+	while ((PRCI_REG(PRCI_DDRPLLCFG) & PLL_LOCK(1)) == 0) {
 		;
+	}
 
 	PRCI_REG(PRCI_DDRPLLOUTDIV) |= OUTDIV_PLLCKE(OUTDIV_PLLCKE_ENA);
 

soc/st/stm32/stm32h7x/soc_m4.c

@@ -51,8 +51,9 @@ static int stm32h7_m4_init(void)
 		 * End of system initialization is reached when CM7 takes HSEM.
 		 */
 		while ((HSEM->RLR[CFG_HW_ENTRY_STOP_MODE_SEMID] & HSEM_R_LOCK)
-				!= HSEM_R_LOCK)
+				!= HSEM_R_LOCK) {
 			;
+		}
 	}
 
 	return 0;