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style: soc: comply with MISRA C:2012 Rule 15.6

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Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This commit is contained in:
Pisit Sawangvonganan 2024-08-16 13:30:48 +07:00 • committed by Henrik Brix Andersen
commit daae40811e
10 changed files with 29 additions and 15 deletions
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6
soc/nxp/imx/imx6sx/soc.c
View file

@ -159,8 +159,9 @@ static void SOC_CacheInit(void)
LMEM_PSCCR = LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK;
LMEM_PSCCR |= LMEM_PSCCR_GO_MASK;
/* Wait until the command completes */
while (LMEM_PSCCR & LMEM_PSCCR_GO_MASK)
while (LMEM_PSCCR & LMEM_PSCCR_GO_MASK) {
;
}
/* Enable system bus cache, enable write buffer */
LMEM_PSCCR = (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK);
barrier_isync_fence_full();
@ -172,8 +173,9 @@ static void SOC_CacheInit(void)
LMEM_PCCCR = LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
LMEM_PCCCR |= LMEM_PCCCR_GO_MASK;
/* Wait until the command completes */
while (LMEM_PCCCR & LMEM_PCCCR_GO_MASK)
while (LMEM_PCCCR & LMEM_PCCCR_GO_MASK) {
;
}
/* Enable code bus cache, enable write buffer */
LMEM_PCCCR = (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
barrier_isync_fence_full();

3
soc/nxp/imx/imx8/adsp/_soc_inthandlers.h
View file

@ -104,12 +104,13 @@ static inline int _xtensa_handle_one_int2(unsigned int mask)
int i = 0;
mask &= XCHAL_INTLEVEL2_MASK;
for (i = 0; i <= 31; i++)
for (i = 0; i <= 31; i++) {
if (mask & BIT(i)) {
mask = BIT(i);
irq = i;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);

3
soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h
View file

@ -104,12 +104,13 @@ static inline int _xtensa_handle_one_int2(unsigned int mask)
int i = 0;
mask &= XCHAL_INTLEVEL2_MASK;
for (i = 0; i <= 31; i++)
for (i = 0; i <= 31; i++) {
if (mask & BIT(i)) {
mask = BIT(i);
irq = i;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);

3
soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h
View file

@ -104,12 +104,13 @@ static inline int _xtensa_handle_one_int2(unsigned int mask)
int i = 0;
mask &= XCHAL_INTLEVEL2_MASK;
for (i = 0; i <= 31; i++)
for (i = 0; i <= 31; i++) {
if (mask & BIT(i)) {
mask = BIT(i);
irq = i;
goto handle_irq;
}
}
return 0;
handle_irq:
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);