diff --git a/dts/arm/renesas/rz/rzg/r9a08g045.dtsi b/dts/arm/renesas/rz/rzg/r9a08g045.dtsi
index 25a8ad3f041..4aa8c8b1698 100644
--- a/dts/arm/renesas/rz/rzg/r9a08g045.dtsi
+++ b/dts/arm/renesas/rz/rzg/r9a08g045.dtsi
@@ -9,6 +9,7 @@
 #include <mem.h>
 #include <freq.h>
 #include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/clock/renesas_rzg_clock.h>
 
 / {
 	compatible = "renesas,r9a08g045";
@@ -40,6 +41,13 @@
 		#clock-cells = <0>;
 	};
 
+	/* External CAN clock - to be overridden by boards that provide it */
+	can_clk: can-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+		#clock-cells = <0>;
+	};
+
 	soc {
 		cpg: clock-controller@41010000 {
 			compatible = "renesas,rz-cpg";
@@ -466,6 +474,32 @@
 			status = "disabled";
 		};
 
+		canfd_global: canfd-global@400c0000 {
+			compatible = "renesas,rz-canfd-global";
+			reg = <0x400c0000 DT_SIZE_K(128)>;
+			interrupts = <373 1>, <374 1>;
+			interrupt-names = "g_err", "g_recc";
+			status = "disabled";
+
+			canfd0: canfd0 {
+				compatible = "renesas,rz-canfd";
+				channel = <0>;
+				interrupts = <375 1>, <377 1>, <379 1>;
+				interrupt-names = "ch_rec", "ch_err", "ch_trx";
+				status = "disabled";
+				clocks = <&cpg RZ_CLOCK_CANFD(0)>;
+			};
+
+			canfd1: canfd1 {
+				compatible = "renesas,rz-canfd";
+				channel = <1>;
+				interrupts = <376 1>, <378 1>, <380 1>;
+				interrupt-names = "ch_rec", "ch_err", "ch_trx";
+				status = "disabled";
+				clocks = <&cpg RZ_CLOCK_CANFD(1)>;
+			};
+		};
+
 		i2c0: i2c@40090000 {
 			compatible = "renesas,rz-riic";
 			channel = <0>;