boards: mimxrt1060_evk: Added SPI support for RT1060
SPI support is available on LPSPI1 and LPSPI3. Both of these require board modifications to expose headers. LPSPI1 is used for testing, and requires that the board have solder jumpers R278, R279, R280, and R281 bridged. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
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5 changed files with 95 additions and 5 deletions
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@ -100,6 +100,8 @@ features:
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+-----------+------------+-------------------------------------+
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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+-----------+------------+-------------------------------------+
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| SPI | on-chip | spi |
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+-----------+------------+-------------------------------------+
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| I2C | on-chip | i2c |
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| I2C | on-chip | i2c |
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+-----------+------------+-------------------------------------+
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+-----------+------------+-------------------------------------+
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| WATCHDOG | on-chip | watchdog |
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| WATCHDOG | on-chip | watchdog |
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@ -132,7 +134,13 @@ The MIMXRT1060 SoC has five pairs of pinmux/gpio controllers.
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| Name | Function | Usage |
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| Name | Function | Usage |
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+===============+=================+===========================+
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+===============+=================+===========================+
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| GPIO_AD_B0_02 | LCD_RST | LCD Display |
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| GPIO_AD_B0_00 | LPSPI1_SCK | SPI |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_01 | LPSPI1_SDO | SPI |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_05 | GPIO | SD Card |
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| GPIO_AD_B0_05 | GPIO | SD Card |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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@ -226,19 +234,23 @@ The MIMXRT1060 SoC has five pairs of pinmux/gpio controllers.
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_10 | ENET_INT | Ethernet |
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| GPIO_AD_B0_10 | ENET_INT | Ethernet |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_SD_B0_00 | USDHC1_CMD | SD Card |
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| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_SD_B0_01 | USDHC1_CLK | SD Card |
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| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_SD_B0_02 | USDHC1_DATA0 | SD Card |
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| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_SD_B0_03 | USDHC1_DATA1 | SD Card |
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| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card |
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| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card |
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| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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.. note::
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In order to use the SPI peripheral on this board, resistors R278, R279,
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R280 and R281 must be populated with zero ohm resistors.
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System Clock
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System Clock
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============
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============
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@ -196,3 +196,11 @@ zephyr_udc0: &usb1 {
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&wdog0 {
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&wdog0 {
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status = "okay";
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status = "okay";
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};
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};
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&lpspi1 {
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status = "okay";
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};
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&lpspi3 {
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status = "okay";
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};
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@ -23,6 +23,7 @@ supported:
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- i2c
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- i2c
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- netif:eth
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- netif:eth
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- sdhc
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- sdhc
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- spi
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- usb_device
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- usb_device
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- kscan:touch
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- kscan:touch
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- dma
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- dma
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@ -312,6 +312,68 @@ static int mimxrt1060_evk_init(const struct device *dev)
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imxrt_usdhc_pinmux_cb_register(mimxrt1060_evk_usdhc_pinmux);
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imxrt_usdhc_pinmux_cb_register(mimxrt1060_evk_usdhc_pinmux);
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#endif
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) && CONFIG_SPI
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
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#error "SPI and SDMMC pins conflict on this board." \
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"Please disable one via KConfig or device tree"
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#else
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/* LPSPI1 SCK, SDO, SDI, PCS0 */
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/* Expose these pins by connecting R278, R279, R280, and R281 on evk board */
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi3), okay) && CONFIG_SPI
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/* LPSPI3 SCK, SDO, SDI, PCS0 */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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return 0;
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return 0;
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}
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}
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@ -0,0 +1,7 @@
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#
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# Copyright (c) 2021, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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CONFIG_SPI_LOOPBACK_DRV_NAME="SPI_1"
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